Designing Techniques for Low Power Multipliers: A Review

Multipliers are fundamental building blocks of all DSP applications. Design of low power, high speed multipliers is carried out to reduce latency and power dissipation of a processing system because switching and critical computations of a multiplier are high, compared to other data path units of a processing architecture. In recent years, a few techniques have been developed that enhance power for accuracy by removing or rearranging multiplier?s blocks. Choosing the proper technique and implementing it can make a big difference in the power dissipation. This is important for low-power battery-operated devices, where longer battery life could be preferred to higher output accuracy. To enhance speed many changes have been made over the existing booth algorithm. In this paper, a simplified comparative study has been presented among SPST based Wallace tree multipliers and other low power multiplier techniques

REVERSIBLE FIR FILTER DESIGNING FOR SPEECH SINGAL PROCESSING

In this paper, a proficient engineering of FIR channel structure is exhibited. For accomplishing low power, reversible logicmode of task is actualized in the plan. Territory overhead isthe tradeoff in the proposed outline. From the amalgamation results,the proposed low power FIR channel engineering offers 18.1 % of intensity sparing when contrasted with the traditional plan. The territory overhead is 2.6% for the proposed engineering

A Reconfigurable Digital Multiplier and 4:2 Compressor Cells Design

With the continually growing use of portable computing devices and increasingly complex software applications, there is a constant push for low power high speed circuitry to support this technology. Because of the high usage and large complex circuitry required to carry out arithmetic operations used in applications such as digital signal processing, there has been a great focus on increasing the efficiency of computer arithmetic circuitry. A key player in the realm of computer arithmetic is the digital multiplier and because of its size and power consumption, it has moved to the forefront of today\u27s research. A digital reconfigurable multiplier architecture will be introduced. Regulated by a 2-bit control signal, the multiplier is capable of double and single precision multiplication, as well as fault tolerant and dual throughput single precision execution. The architecture proposed in this thesis is centered on a recursive multiplication algorithm, where a large multiplication is carried out using recursions of simpler submultiplier modules. Within each sub-multiplier module, instead of carry save adder arrays, 4:2 compressor rows are utilized for partial product reduction, which present greater efficiency, thus result in lower delay and power consumption of the whole multiplier. In addition, a study of various digital logic circuit styles are initially presented, and then three different designs of 4:2 compressor in Domino Logic are presented and simulation results confirm the property of proposed design in terms of delay, power consumption and operation frequenc

A comparative study of novel variable set multiplier scheme and other column compression multipliers

The extensive use of multipliers in high-performance processors has been driving the demand for low-power, high-speed multipliers. This report presents a novel fast multiplier scheme that performs reduction based on non-uniform grouping in the partial product matrix. In every stage, the partial products are grouped into sets of variable heights before reduction. The algorithm is presented and compared with Wallace, Dadda, and Reduced Area Multipliers in terms of gate complexity, delay, interconnects and power utilization for 4-bit, 7-bit, 8-bit and 12-bit versions. The proposed design is observed to have a gate count of 3% lower than Wallace multipliers, comparable to Dadda in most of the cases but slightly higher than Reduced Area multipliers. To fulfill the study, a 12-bit version of each multiplier was implemented in structural Verilog with basic gates and synthesized using Xilinx Vivado. The net cell usage statistics and the power utilization values were extracted and compared. It was observed that the proposed design has better power efficiency than the other multipliers for the examined cases.Electrical and Computer Engineerin

Low-Power, Low-Cost, & High-Performance Digital Designs : Multi-bit Signed Multiplier design using 32nm CMOS Technology

Binary multipliers are ubiquitous in digital hardware. Digital multipliers along with the adders play a major role in computing, communicating, and controlling devices. Multipliers are used majorly in the areas of digital signal and image processing, central processing unit (CPU) of the computers, high-performance and parallel scientific computing, machine learning, physical layer design of the communication equipment, etc. The predominant presence and increasing demand for low-power, low-cost, and high-performance digital hardware led to this work of developing optimized multiplier designs. Two optimized designs are proposed in this work. One is an optimized 8 x 8 Booth multiplier architecture which is implemented using 32nm CMOS technology. Synthesis (pre-layout) and post-layout results show that the delay is reduced by 24.7% and 25.6% respectively, the area is reduced by 5.5% and 15% respectively, the power consumption is reduced by 21.5% and 26.6% respectively, and the area-delay-product is reduced by 28.8% and 36.8% respectively when compared to the performance results obtained for the state-of-the-art 8 x 8 Booth multiplier designed using 32nm CMOS technology with 1.05 V supply voltage at 500 MHz input frequency. Another is a novel radix-8 structure with 3-bit grouping to reduce the number of partial products along with the effective partial product reduction schemes for 8 x 8, 16 x 16, 32 x 32, and 64 x 64 signed multipliers. Comparing the performance results of the (synthesized, post-layout) designs of sizes 32 x 32, and 64 x 64 based on the simple novel radix-8 structure with the estimated performance measurements for the optimized Booth multiplier design presented in this work, reduction in delay by (2.64%, 0.47%) and (2.74%, 18.04%) respectively, and reduction in area-delay-product by (12.12%, -5.17%) and (17.82%, 12.91%) respectively can be observed. With the use of the higher radix structure, delay, area, and power consumption can be further reduced. Appropriate adder deployment, further exploring the optimized grouping or compression strategies, and applying more low-power design techniques such as power-gating, multi-Vt MOS transistor utilization, multi-VDD domain creation, etc., help, along with the higher radix structures, realizing the more efficient multiplier designs

Investigation into arithmetic sub-cells for digital multiplication.

A study of several low-power and high-speed (3,2) counter designs is initially presented, then based on these findings, a new 4:2 compressor design is introduced and proven against other existing and newly devised 4:2 compressors using various logic styles. The results obtained with regards to speed, power and size were used to categorize the circuits in terms of individual and cumulative performance characteristics. A complete 16-bit multiplier design which uses a highly efficient layout scheme along with the top performing 4:2 compressor form the above study is presented. A second multiplier using industry standard (3,2) counters in a 4:2 compressor configuration following the same optimized layout scheme is constructed and simulated as a benchmark for comparison to the new design. In order to carry out this investigation, the proper methodology for power measurement in pass-logic circuits was developed and is presented within. This survey offers an unpartisan approach to power measurement, and an accurate reflection of the vantage points of each logic style. (Abstract shortened by UMI.)Dept. of Electrical and Computer Engineering. Paper copy at Leddy Library: Theses & Major Papers - Basement, West Bldg. / Call Number: Thesis2005 .H69. Source: Masters Abstracts International, Volume: 44-03, page: 1453. Thesis (M.A.Sc.)--University of Windsor (Canada), 2005

Total delay optimization for column reduction multipliers considering non-uniform arrival times to the final adder

textColumn Reduction Multiplier techniques provide the fastest multiplier designs and involve three steps. First, a partial product array of terms is formed by logically ANDing each bit of the multiplier with each bit of the multiplicand. Second, adders or counters are used to reduce the number of terms in each bit column to a final two. This activity is commonly described as column reduction and occurs in multiple stages. Finally, some form of carry propagate adder (CPA) is applied to the final two terms in order to sum them to produce the final product of the multiplication. Since forming the partial products, in the first step, is simply forming an array of the logical AND's of two bits, there is little opportunity for delay improvement for the first step. There has been much work done in optimizing the reduction stages for column multipliers in the second reduction step. All of the reduction approaches of the second step result in non-uniform arrival times to the input of the final carry propagate adder in the final step. The designs for carry propagate adders have been done assuming that the input bits all have the same arrival time. It is not evident that the non-uniform arrival times from the columns impacts the performance of the multiplier. A thorough analysis of the several column reduction methods and the impact of carry propagate adder designs, along with the column reduction design step, to provide the fastest possible final results, for an array of multiplier widths has not been undertaken. This dissertation investigates the design impact of three carry propagate adders, with different performance attributes, on the final delay results for four column reduction multipliers and suggests general ways to optimize the total delay for the multipliers.Electrical and Computer Engineerin