Influence of jitter on limit cycles in bang-bang clock and data recovery circuits

In bang-bang (BB) clock and data recovery circuits (CDR) limit cycles can occur, but these limit cycles are undesired for a good operation of the BB-CDR. Surprisingly, however, a little bit of noise in the system is beneficial, because it will quench the limit cycles. Until now, authors have always assumed that there is enough noise in a BB-CDR such that no limit cycle occurs. In this work, a pseudo-linear analysis based on describing functions is used to investigate this. In particular, the relationship between the input noise and the amplitude of eventual limit cycles is investigated. An important result of the theory is that it allows to quantify the influence of the different loop parameters on the minimal amount of input jitter needed to destroy the limit cycle. Additionally, for the case that there is not enough noise, the worst case amplitude of the limit cycle (which is unavoidable in this case) is quantified as well. The presented analysis exhibits excellent matching with time domain simulations and leads to very simple analytical expressions

다이렉트 경로를 이용한 5/8GHz 듀얼 모드 All-Digital Phase-Locked Loop의 설계

학위논문 (석사)-- 서울대학교 대학원 : 공과대학 전기·정보공학부, 2019. 2. 정덕균.최근 데이터의 전송 속도가 비약적으로 증가함에 따라 데이터 처리 방식이 다양하게 연구되었고 여러 방식에 따른 고속의 송수신기 설계가 중요시되고 있다. 그 중에서도 Clock 신호를 합성하는 역할인 Phase-Locked Loop (PLL)에 대한 연구가 활발히 진행되고 있다. 특히 패시브 소자를 Loop Filter에 사용해야 하는 Analog PLL보다는 PVT 변화에 둔감하고 Programmable 하다는 장점을 가진 All Digital PLL (AD-PLL)에 대한 관심도가 높아지고 있다. 본 논문에서는 Peripheral Component Interconnect Express Memory interface (PCIe) 지원을 위한 32Gbps Serial Link에 Common Clock 신호를 제공하는 5/8 GHz 듀얼 모드 AD-PLL을 제안한다. 이전 세대와의 호환성을 위해 넓은 동작 영역을 갖고 모드 선택이 가능한 듀얼 모드 Digitally Controlled Oscillator (DCO)를 사용하였고 설계 전 Digital 방식으로 변환함에 따라 발생하는 Quantization Noise에 대해 분석하고 Matlab, Verilog Behavioral Simulation을 통해 출력의 Phase Noise와 RMS Jitter 값을 예측해 볼 수 있었다. 또한 Reference Clock의 한 주기 이내에 정보가 Update되지 못하는 Loop Delay의 문제를 해결하기 위해 Digital Loop Filter (DLF)의 처리 과정을 거치지 않고 Time to Digital Converter (TDC)의 출력을 DCO에 바로 전달해 줄 수 있는 다이렉트 경로를 제안하였다. 설계된 회로는 TSMC 사의 65nm 공정으로 구현되었고 AD-PLL의 전체 유효 면적은 Decoupling Cap을 제외하고 420um·300um이며 측정된 출력 Clock 신호의 RMS Jitter값은 8GHz 모드에서 357fs, 5GHz 모드에서 394fs이다. AD-PLL의 동작 주파수는 PCIe Spec의 다양한 모드를 지원하기 위해 외부의 입력 모드 신호에 따라서 5GHz/8GHz의 High/Low Band를 지원하고 1.2V의 공급 전압에서 Repeater를 제외하고 8GHz 모드에서는 총 18.26mW, 5GHz 모드에서는 총 12.06mW의 Power를 소비한다.As data transmission speed has increased in recent years, a variety of data processing techniques have been studied and high-speed transceiver has become important. Above all, Phase-Locked Loop (PLL), which synthesizes high frequency clock signal, is one of the important parts. In particular, All-Digital PLL(AD-PLL), which has advantage of programmability and PVT tolerance, is replacing Analog PLL that requires passive element utilization. This thesis presents a 5/8GHz dual mode AD-PLL to provide common clock signal to 32Gbps serial link to support Peripheral Component Interconnect Express(PCIe) PHY. For compatibility with previous generations and wide operating region, AD-PLL uses dual mode Digitally Controlled Oscillator(DCO). Before an actual design, output RMS Jitter, Phase Noise of AD-PLL and quantization error resulting from digital conversion are calculated and analyzed by using Matlab, Verilog behavioral simulation in a short time. In addition, the output of Time-to-Digital Converter(TDC) is directly delivered to the DCO without Digital Loop Filter(DLF) using direct path to solve loop delay issue where information cant be updated within a cycle of reference clock. The proposed AD-PLL is fabricated in 65nm CMOS process and effective area of AD-PLL is 420um·300um and the measured RMS Jitter is 357fs at 8GHz mode, 394fs at 5GHz mode. Also, proposed AD-PLL supports the low/high band(5/8GHz) to be compatible with the various modes of PCIe spec. Power dissipation is 18.26mW at 8GHz mode, 12.06mW at 5GHz mode in 1.2V supply voltage domain excluding repeater.제 1 장 서 론 1 1.1 연구의 배경 1 1.2 논문의 구성 3 제 2 장 Basics of AD-PLL 4 2.1 Introduction of AD-PLL 4 2.2 Building Blocks of AD-PLL 5 2.2.1 Time to Digital Converter 6 2.2.2 Digital Loop Filter 8 2.2.3 Digitally Controlled Oscillator 10 2.3 Phase Noise Analysis 13 2.4 Loop Delay 18 제 3 장 Design of AD-PLL 22 3.1 Design Consideration 22 3.2 Overall Architecture 22 3.3 Phase Frequency Detectable TDC 24 3.4 Digital Loop Filter 27 3.5 Digitally Controlled Oscillator 30 3.6 Direct Path 33 3.7 Level Shifter and Divider 36 3.8 Clock Tree 39 제 4 장 Measurement and Simulation Results 41 4.1 Measurement Setup 41 4.2 Die Photomicrograph 43 4.3 Frequency Tracking Behavior 44 4.4 Clock Distribution 46 4.5 Phase Noise and Spur 47 4.6 Performance Summary 53 제 5 장 Conclusion 55 참고 문헌 56 Abstract 59Maste

Analysis and Design of Low-Jitter Digital Bang-Bang Phase-Locked Loops

Digital phase-locked loops based on bang-bang phase detectors are attractive candidates for low-jitter clock-frequency multiplication. Unfortunately, the coarse quantization of phase error makes these systems prone to the generation of limit cycles appearing as unwanted spurs in the spectrum. The random noise contributed by building blocks and acting as dithering signal can eliminate those spurs. The quantitative analysis of those phenomena becomes more involved when a DCO with relaxed intrinsic resolution, such as a ΔΣ-DCO is employed, and when practical spectra of random noise sources are considered. In this work, the expression of jitter is calculated in closed-form taking into account the quantization, introduced by both phase detector and DCO, and the phase noise of DCO, with both 1/f^2 and 1/^3 components. Combining these results, a closed-form expression of the total output jitter as a function of loop parameters and noise sources is developed which suggests a minimum-jitter design strategy. The proposed analysis and optimization are validated both numerically and experimentally on a 320-MHz digital bang-bang PLL fabricated in a 65-nm CMOS process

LOW-JITTER AND LOW-SPUR RING-OSCILLATOR-BASED PHASE-LOCKED LOOPS

Department of Electrical EngineeringIn recent years, ring-oscillator based clock generators have drawn a lot of attention due to the merits of high area efficiency, potentially wide tuning range, and multi-phase generation. However, the key challenge is how to suppress the poor jitter of ring oscillators. There have been many efforts to develop a ring-oscillator-based clock generator targeting very low-jitter performance. However, it remains difficult for conventional architectures to achieve both low RMS jitter and low levels of reference spurs concurrently while having a high multiplication factor. In this dissertation, a time-domain analysis is presented that provides an intuitive understanding of RMS jitter calculation of the clock generators from their phase-error correction mechanisms. Based on this analysis, we propose new designs of a ring-oscillator-based PLL that addresses the challenges of prior-art ring-based architectures. This dissertation introduces a ring-oscillator-based PLL with the proposed fast phase-error correction (FPEC) technique, which emulates the phase-realignment mechanism of an injection-locked clock multiplier (ILCM). With the FPEC technique, the phase error of the voltage-controlled oscillator (VCO) is quickly removed, achieving ultra-low jitter. In addition, in the transfer function of the proposed architecture, an intrinsic integrator is involved since it is naturally based on a PLL topology. The proposed PLL can thus have low levels of reference spurs while maintaining high stability even for a large multiplication factor. Furthermore, it presents another design of a digital PLL embodying the FPEC technique (or FPEC DPLL). To overcome the problem of a conventional TDC, a low-power optimally-spaced (OS) TDC capable of effectively minimizing the quantization error is presented. In the proposed FPEC DPLL, background digital controllers continuously calibrate the decision thresholds and the gain of the error correction by the loop to be optimal, thus dramatically reducing the quantization error. Since the proposed architecture is implemented in a digital fashion, the variables defining the characteristics of the loop can be easily estimated and calibrated by digital calibrators. As a result, the performances of an ultra-low jitter and the figure-of-merit can be achieved.clos