High linearity analog and mixed-signal integrated circuit design

Linearity is one of the most important specifications in electrical circuits.;In Chapter 1, a ladder-based transconductance networks has been adopted first time to build a low distortion analog filters for low frequency applications. This new technique eliminated the limitation of the application with the traditional passive resistors for low frequency applications. Based on the understanding of this relationship, a strategy for designing high linear analog continuous-time filters has been developed. According to our strategy, a prototype analog integrated filter has been designed and fabricated with AMI05 0.5 um standard CMOS process. Experimental results proved this technique has the ability to provide excellent linearity with very limited active area.;In Chapter 2, the relationships between the transconductance networks and major circuit specifications have been explored. The analysis reveals the trade off between the silicon area saved by the transconductance networks and the some other important specifications such as linearity, noise level and the process variations of the overall circuit. Experimental results of discrete component circuit matched very well with our analytical outcomes to predict the change of linearity and noise performance associated with different transconductance networks.;The Chapter 3 contains the analysis and mathematical proves of the optimum passive area allocations for several most popular analog active filters. Because the total area is now manageable by the technique introduced in the Chapter 1, the further reduce of the total area will be very important and useful for efficient utilizing the silicon area, especially with the today\u27s fast growing area efficiency of the highly density digital circuits. This study presents the mathematical conclusion that the minimum passive area will be achieved with the equalized resistor and capacitor.;In the Chapter 4, a well recognized and highly honored current division circuit has been studied. Although it was claimed to be inherently linear and there are over 60 published works reported with high linearity based on this technique, our study discovered that this current division circuit can achieve, if proper circuit condition being managed, very limited linearity and all the experimental verified performance actually based on more general circuit principle. Besides its limitation, however, we invented a novel current division digital to analog converter (DAC) based on this technique. Benefiting from the simple circuit structure and moderate good linearity, a prototype 8-bit DAC was designed in TSMC018 0.2 um CMOS process and the post layout simulations exhibited the good linearity with very low power consumption and extreme small active area.;As the part of study of the output stage for the current division DAC discussed in the Chapter 4, a current mirror is expected to amplify the output current to drive the low resistive load. The strategy of achieving the optimum bandwidth of the cascode current mirror with fixed total current gain is discussed in the Chapter 5.;Improving the linearity of pipeline ADC has been the hottest and hardest topic in solid-state circuit community for decade. In the Chapter 6, a comprehensive study focus on the existing calibration algorithms for pipeline ADCs is presented. The benefits and limitations of different calibration algorithms have been discussed. Based on the understanding of those reported works, a new model-based calibration is delivered. The simulation results demonstrate that the model-based algorithms are vulnerable to the model accuracy and this weakness is very hard to be removed. From there, we predict the future developments of calibration algorithms that can break the linearity limitations for pipelined ADC. (Abstract shortened by UMI.

Time-domain optimization of amplifiers based on distributed genetic algorithms

Thesis presented in partial fulfillment of the requirements for the degree of Doctor of Philosophy in the subject of Electrical and Computer EngineeringThe work presented in this thesis addresses the task of circuit optimization, helping the designer facing the high performance and high efficiency circuits demands of the market and technology evolution. A novel framework is introduced, based on time-domain analysis, genetic algorithm optimization, and distributed processing. The time-domain optimization methodology is based on the step response of the amplifier. The main advantage of this new time-domain methodology is that, when a given settling-error is reached within the desired settling-time, it is automatically guaranteed that the amplifier has enough open-loop gain, AOL, output-swing (OS), slew-rate (SR), closed loop bandwidth and closed loop stability. Thus, this simplification of the circuit‟s evaluation helps the optimization process to converge faster. The method used to calculate the step response expression of the circuit is based on the inverse Laplace transform applied to the transfer function, symbolically, multiplied by 1/s (which represents the unity input step). Furthermore, may be applied to transfer functions of circuits with unlimited number of zeros/poles, without approximation in order to keep accuracy. Thus, complex circuit, with several design/optimization degrees of freedom can also be considered. The expression of the step response, from the proposed methodology, is based on the DC bias operating point of the devices of the circuit. For this, complex and accurate device models (e.g. BSIM3v3) are integrated. During the optimization process, the time-domain evaluation of the amplifier is used by the genetic algorithm, in the classification of the genetic individuals. The time-domain evaluator is integrated into the developed optimization platform, as independent library, coded using C programming language. The genetic algorithms have demonstrated to be a good approach for optimization since they are flexible and independent from the optimization-objective. Different levels of abstraction can be optimized either system level or circuit level. Optimization of any new block is basically carried-out by simply providing additional configuration files, e.g. chromosome format, in text format; and the circuit library where the fitness value of each individual of the genetic algorithm is computed. Distributed processing is also employed to address the increasing processing time demanded by the complex circuit analysis, and the accurate models of the circuit devices. The communication by remote processing nodes is based on Message Passing interface (MPI). It is demonstrated that the distributed processing reduced the optimization run-time by more than one order of magnitude. Platform assessment is carried by several examples of two-stage amplifiers, which have been optimized and successfully used, embedded, in larger systems, such as data converters. A dedicated example of an inverter-based self-biased two-stage amplifier has been designed, laid-out and fabricated as a stand-alone circuit and experimentally evaluated. The measured results are a direct demonstration of the effectiveness of the proposed time-domain optimization methodology.Portuguese Foundation for the Science and Technology (FCT

Low-Power Slew-Rate Boosting Based 12-Bit Pipeline ADC Utilizing Forecasting Technique in the Sub-ADCS

The dissertation presents architecture and circuit solutions to improve the power efficiency of high-speed 12-bit pipelined ADCs in advanced CMOS technologies. First, the 4.5bit algorithmic pipelined front-end stage is proposed. It is shown that the algorithmic pipelined ADC requires a simpler sub-ADC and shows lower sensitivity to the Multiplying DAC (MDAC) errors and smaller area and power dissipation in comparison to the conventional multi-bit per stage pipelined ADC. Also, it is shown that the algorithmic pipelined architecture is more tolerant to capacitive mismatch for the same input-referred thermal noise than the conventional multi-bit per stage architecture. To take full advantage of these properties, a modified residue curve for the pipelined ADC is proposed. This concept introduces better linearity compared with the conventional residue curve of the pipelined ADC; this approach is particularly attractive for the digitization of signals with large peak to average ratio such as OFDM coded signals. Moreover, the minimum total required transconductance for the different architectures of the 12-bit pipelined ADC are computed. This helps the pipelined ADC designers to find the most power-efficient architecture between different topologies based on the same input-referred thermal noise. By employing this calculation, the most power efficient architecture for realizing the 12-bit pipelined ADC is selected. Then, a technique for slew-rate (SR) boosting in switched-capacitor circuits is proposed in the order to be utilized in the proposed 12-bit pipelined ADC. This technique makes use of a class-B auxiliary amplifier that generates a compensating current only when high slew-rate is demanded by large input signal. The proposed architecture employs simple circuitry to detect the need of injecting current at the output load by implementing a Pre-Amp followed by a class-B amplifier, embedded with a pre-defined hysteresis, in parallel with the main amplifier to boost its slew phase. The proposed solution requires small static power since it does not need high dc-current at the output stage of the main amplifier. The proposed technique is suitable for high-speed low-power multi-bit/stage pipelined ADC applications. Both transistor-level simulations and experimental results in TSMC 40nm technology reduces the slew-time for more than 45% and shorts the 1% settling time by 28% when used in a 4.5bit/stage pipelined ADC; power consumption increases by 20%. In addition, the technique of inactivating and disconnecting of the sub-ADC’s comparators by forecasting the sign of the sampled input voltage is proposed in the order to reduce the dynamic power consumption of the sub-ADCs in the proposed 12-bit pipelined ADC. This technique reduces the total dynamic power consumption more than 46%. The implemented 12-bit pipelined ADC achieves an SNDR/SFDR of 65.9/82.3 dB at low input frequencies and a 64.1/75.5 dB near Nyquist frequency while running at 500 MS/s. The pipelined ADC prototype occupies an active area of 0.9 mm^2 and consumes 18.16 mW from a 1.1 V supply, resulting in a figure of merit (FOM) of 22.4 and a 27.7 fJ/conversion-step at low-frequency and Nyquist frequency, respectively

Oscillation-based DFT for Second-order Bandpass OTA-C Filters

This document is the Accepted Manuscript version. Under embargo until 6 September 2018. The final publication is available at Springer via https://doi.org/10.1007/s00034-017-0648-9.This paper describes a design for testability technique for second-order bandpass operational transconductance amplifier and capacitor filters using an oscillation-based test topology. The oscillation-based test structure is a vectorless output test strategy easily extendable to built-in self-test. The proposed methodology converts filter under test into a quadrature oscillator using very simple techniques and measures the output frequency. Using feedback loops with nonlinear block, the filter-to-oscillator conversion techniques easily convert the bandpass OTA-C filter into an oscillator. With a minimum number of extra components, the proposed scheme requires a negligible area overhead. The validity of the proposed method has been verified using comparison between faulty and fault-free simulation results of Tow-Thomas and KHN OTA-C filters. Simulation results in 0.25μm CMOS technology show that the proposed oscillation-based test strategy for OTA-C filters is suitable for catastrophic and parametric faults testing and also effective in detecting single and multiple faults with high fault coverage.Peer reviewedFinal Accepted Versio

A Novel Current-Mode Full-Wave Rectifier Based on One CDTA and Two Diodes

Precision rectifiers are important building blocks for analog signal processing. The traditional approach based on diodes and operational amplifiers (OpAmps) exhibits undesirable effects caused by limited OpAmp slew rate and diode commutations. In the paper, a full-wave rectifier based on one CDTA and two Schottky diodes is presented. The PSpice simulation results are included

Low-Power Slew-Rate Boosting Based 12-Bit Pipeline ADC Utilizing Forecasting Technique in the Sub-ADCS

The dissertation presents architecture and circuit solutions to improve the power efficiency of high-speed 12-bit pipelined ADCs in advanced CMOS technologies. First, the 4.5bit algorithmic pipelined front-end stage is proposed. It is shown that the algorithmic pipelined ADC requires a simpler sub-ADC and shows lower sensitivity to the Multiplying DAC (MDAC) errors and smaller area and power dissipation in comparison to the conventional multi-bit per stage pipelined ADC. Also, it is shown that the algorithmic pipelined architecture is more tolerant to capacitive mismatch for the same input-referred thermal noise than the conventional multi-bit per stage architecture. To take full advantage of these properties, a modified residue curve for the pipelined ADC is proposed. This concept introduces better linearity compared with the conventional residue curve of the pipelined ADC; this approach is particularly attractive for the digitization of signals with large peak to average ratio such as OFDM coded signals. Moreover, the minimum total required transconductance for the different architectures of the 12-bit pipelined ADC are computed. This helps the pipelined ADC designers to find the most power-efficient architecture between different topologies based on the same input-referred thermal noise. By employing this calculation, the most power efficient architecture for realizing the 12-bit pipelined ADC is selected. Then, a technique for slew-rate (SR) boosting in switched-capacitor circuits is proposed in the order to be utilized in the proposed 12-bit pipelined ADC. This technique makes use of a class-B auxiliary amplifier that generates a compensating current only when high slew-rate is demanded by large input signal. The proposed architecture employs simple circuitry to detect the need of injecting current at the output load by implementing a Pre-Amp followed by a class-B amplifier, embedded with a pre-defined hysteresis, in parallel with the main amplifier to boost its slew phase. The proposed solution requires small static power since it does not need high dc-current at the output stage of the main amplifier. The proposed technique is suitable for high-speed low-power multi-bit/stage pipelined ADC applications. Both transistor-level simulations and experimental results in TSMC 40nm technology reduces the slew-time for more than 45% and shorts the 1% settling time by 28% when used in a 4.5bit/stage pipelined ADC; power consumption increases by 20%. In addition, the technique of inactivating and disconnecting of the sub-ADC’s comparators by forecasting the sign of the sampled input voltage is proposed in the order to reduce the dynamic power consumption of the sub-ADCs in the proposed 12-bit pipelined ADC. This technique reduces the total dynamic power consumption more than 46%. The implemented 12-bit pipelined ADC achieves an SNDR/SFDR of 65.9/82.3 dB at low input frequencies and a 64.1/75.5 dB near Nyquist frequency while running at 500 MS/s. The pipelined ADC prototype occupies an active area of 0.9 mm^2 and consumes 18.16 mW from a 1.1 V supply, resulting in a figure of merit (FOM) of 22.4 and a 27.7 fJ/conversion-step at low-frequency and Nyquist frequency, respectively

IDDQ Testing of Low Voltage CMOS Operational Transconductance Amplifier

The paper describes the design for testability (DFT) of low voltage two stage operational transconductance amplifiers based on quiescent power supply current (IDDQ) testing. IDDQ testing refers to the integral circuit testing method based upon measurement of steady state power supply current for testing both digital as well as analog VLSI circuit. A built in current sensor, which introduces insignificant performance degradation of the circuit-under-test, has been proposed to monitor the power supply quiescent current changes in the circuit under test. Moreover, the BICS requires neither an external voltage reference nor a current source and able to detect, identify and localize the circuit faults. Hence the BICS requires less area and is more efficient than the conventional current sensors. The testability has also been enhanced in the testing procedure using a simple fault-injection technique. Both bridging and open faults have been analyzed in proposed work by using n-well 0.18µm CMOS technology

DESIGN OF TWO STAGE BULK-DRIVEN OPERATIONAL TRANSCONDUCTANCE AMPLIFIER (OTA) WITH A HIGH GAIN FOR LOW VOLTAGE APPLICATION

An Operational Transconductance Amplifier (further abbreviated as OTA) is a voltage controlled current source used to produce an output current proportional to the input voltage. A schematic architecture for a 180nm OTA is presented in this thesis with the goal of improving the open-loop gain for a 0.9V supply voltage with a rail-to-rail bulk-driven input stage. Results show an open loop gain 97.14 dB with a power consumption of 3.33uW. An OTA with over 90 dB open loop gain and lower power consumption is highly suitable for low-voltage applications. The slew rate of the OTA is 0.05V/uS with a unity-gain bandwidth of 8.4MHz. A 10uA ideal bias current reference is utilized for the design. The phase margin is around 49.2 degrees. The threshold voltage for a 180nm N-channel Metal Oxide Semiconductor (also known as NMOS) device is around 400mV which restricts the low voltage applications in most amplifier circuits. The fourth terminal (bulk) of the MOS device is utilized to optimize the voltage headroom (Vds). The bulk terminal uses a much lesser source to drain voltage than the gate-driven transistors, and the transistors remain ON with an input voltage as low as 0.1V. A bulk-driven input stage ensures the amplification in the subthreshold region (input signal less than the threshold voltage of the MOS device). However, even with the bulk input MOS device, a rail-to-rail input stage is employed to improve the dynamic range for the input signal from 0V to 0.9V with a supply voltage of 0.9V. The fluctuation in open loop gain concerning the change in input signal in the published research is because of the constant instability in the intrinsic transconductance of the input devices. A possible solution is presented in this thesis by adding a second dominant pole to the circuit (i.e., second stage for the OTA), which reduces the dependency of intrinsic transconductance (bulk-driven device) on the total open loop gain of the amplifier. Thus, a significant gain of 97.14 dB with minimal fluctuations is achieved. Furthermore, adding a second stage improves the gain by distributing the dependency of the gain due to the first stage to both poles in the circuit. Hence, the problem of fluctuating transconductance of the input stage is resolved by the constant intrinsic transconductance of the MOS near the second pole (M19). To improve the gain, a folded cascoded amplifier connected with the input stage results in a better impedance (in the first stage) known as the gain stage. In the second stage, a large PMOS common source amplifier gives a good output current compared to the input stage to enhance the output swing and drive a purely capacitive load of 0.5pF. Furthermore, a miller capacitance is used to compensate for the frequency between the first and the second stage and improving the unity-gain bandwidth. An additional biasing circuit in the second stage amplifies the current output of the first stage and thus improving the slew rate of the entire device. In addition, the biasing circuit resolves the biasing issues for the second-stage common-source amplifier. It improves the output swing of the device to obtain a clean/undistorted output waveform. All the simulations are carried out in the LTSpice simulation tool to test the waveforms and bode plot for open loop gain and phase margin (49.2 degrees) at different processes (slow, typical, and fast), input voltages (0-0.9V), supply voltage (0.8V, 0.9V, 1.0V) and temperatures (-10 to 100 degree C)

Ultra-Low-Voltage IC Design Methods

The emerging nanoscale technologies inherently offer transistors working with low voltage levels and are optimized for low-power operation. However, these technologies lack quality electronic components vital for reliable analog and/or mixed-signal design (e.g., resistor, capacitor, etc.) as they are predominantly used in high-performance digital designs. Moreover, the voltage headroom, ESD properties, the maximum current densities, parasitic effects, process fluctuations, aging effects, and many other parameters are superior in verified-by-time CMOS processes using planar transistors. This is the main reason, why low-voltage, low-power high-performance analog and mixed-signal circuits are still being designed in mature process nodes. In the proposed chapter, we bring an overview of main challenges and design techniques effectively applicable for ultra-low-voltage and low-power analog integrated circuits in nanoscale technologies. New design challenges and limitations linked with a low value of the supply voltage, the process fluctuation, device mismatch, and other effects are discussed. In the later part of the chapter, conventional and unconventional design techniques (bulk-driven approach, floating-gate, dynamic threshold, etc.) to design analog integrated circuits towards ultra-low-voltage systems and applications are described. Examples of ultra-low-voltage analog ICs blocks (an operational amplifier, a voltage comparator, a charge pump, etc.) designed in a standard CMOS technology using the unconventional design approach are presented