A design for testability study on a high performance automatic gain control circuit.

A comprehensive testability study on a commercial automatic gain control circuit is presented which aims to identify design for testability (DfT) modifications to both reduce production test cost and improve test quality. A fault simulation strategy based on layout extracted faults has been used to support the study. The paper proposes a number of DfT modifications at the layout, schematic and system levels together with testability. Guidelines that may well have generic applicability. Proposals for using the modifications to achieve partial self test are made and estimates of achieved fault coverage and quality levels presente

Regression modeling for digital test of ΣΔ modulators

The cost of Analogue and Mixed-Signal circuit testing is an important bottleneck in the industry, due to timeconsuming verification of specifications that require state-ofthe- art Automatic Test Equipment. In this paper, we apply the concept of Alternate Test to achieve digital testing of converters. By training an ensemble of regression models that maps simple digital defect-oriented signatures onto Signal to Noise and Distortion Ratio (SNDR), an average error of 1:7% is achieved. Beyond the inference of functional metrics, we show that the approach can provide interesting diagnosis information.Ministerio de Educación y Ciencia TEC2007-68072/MICJunta de Andalucía TIC 5386, CT 30

Concurrent Backscatter Streaming from Batteryless and Wireless Sensor Tags with Multiple Subcarrier Multiple Access

This paper proposes a novel multiple access method that enables concurrent sensor data streaming from multiple batteryless, wireless sensor tags. The access method is a pseudo-FDMA scheme based on the subcarrier backscatter communication principle, which is widely employed in passive RFID and radar systems. Concurrency is realized by assigning a dedicated subcarrier to each sensor tag and letting all sensor tags backscatter simultaneously. Because of the nature of the subcarrier, which is produced by constant rate switching of antenna impedance without any channel filter in the sensor tag, the tag-to-reader link always exhibits harmonics. Thus, it is important to reject harmonics when concurrent data streaming is required. This paper proposes a harmonics rejecting receiver to allow simultaneous multiple subcarrier usage. This paper particularly focuses on analog sensor data streaming which minimizes the functional requirements on the sensor tag and frequency bandwidth. The harmonics rejection receiver is realized by carefully handling group delay and phase delay of the subcarrier envelope and the carrier signal to accurately produce replica of the harmonics by introducing Hilbert and inverse Hilbert transformations. A numerical simulator with Simulink and a hardware implementation with USRP and LabVIEW have been developed. Simulations and experiments reveal that even if the CIR before harmonics rejection is 0dB, the proposed receiver recovers the original sensor data with over 0.98 cross-correlation

Use of high performance networks and supercomputers for real-time flight simulation

In order to meet the stringent time-critical requirements for real-time man-in-the-loop flight simulation, computer processing operations must be consistent in processing time and be completed in as short a time as possible. These operations include simulation mathematical model computation and data input/output to the simulators. In 1986, in response to increased demands for flight simulation performance, NASA's Langley Research Center (LaRC), working with the contractor, developed extensions to the Computer Automated Measurement and Control (CAMAC) technology which resulted in a factor of ten increase in the effective bandwidth and reduced latency of modules necessary for simulator communication. This technology extension is being used by more than 80 leading technological developers in the United States, Canada, and Europe. Included among the commercial applications are nuclear process control, power grid analysis, process monitoring, real-time simulation, and radar data acquisition. Personnel at LaRC are completing the development of the use of supercomputers for mathematical model computation to support real-time flight simulation. This includes the development of a real-time operating system and development of specialized software and hardware for the simulator network. This paper describes the data acquisition technology and the development of supercomputing for flight simulation

Spacelab data analysis and interactive control study

The study consisted of two main tasks, a series of interviews of Spacelab users and a survey of data processing and display equipment. Findings from the user interviews on questions of interactive control, downlink data formats, and Spacelab computer software development are presented. Equipment for quick look processing and display of scientific data in the Spacelab Payload Operations Control Center (POCC) was surveyed. Results of this survey effort are discussed in detail, along with recommendations for NASA development of several specific display systems which meet common requirements of many Spacelab experiments

Application of technology developed for flight simulation at NASA. Langley Research Center

In order to meet the stringent time-critical requirements for real-time man-in-the-loop flight simulation, computer processing operations including mathematical model computation and data input/output to the simulators must be deterministic and be completed in as short a time as possible. Personnel at NASA's Langley Research Center are currently developing the use of supercomputers for simulation mathematical model computation for real-time simulation. This, coupled with the use of an open systems software architecture, will advance the state-of-the-art in real-time flight simulation

Analog neural networks for real-time constrained optimization

Architectures and circuit techniques for implementing general piecewise constrained optimization problems using VLSI techniques are explored. Discrete-time analog techniques are considered due to their inherent accuracy, programmability, and reconfigurability. A general architecture for minimizing piecewise functions by using gradient schemes is introduced. Switched-capacitor (SC) building blocks featuring improved characteristics in terms of area occupation and operation speed are presented. The implementation of the architectures by using the newest switched-current techniques is discussed. The layout of a 3-μm CMOS SC prototype for a quadratic optimization problem with linear constraints is given

A RISC-V Vector Processor With Simultaneous-Switching Switched-Capacitor DC-DC Converters in 28 nm FDSOI

This work demonstrates a RISC-V vector microprocessor implemented in 28 nm FDSOI with fully integrated simultaneous-switching switched-capacitor DC-DC (SC DC-DC) converters and adaptive clocking that generates four on-chip voltages between 0.45 and 1 V using only 1.0 V core and 1.8 V IO voltage inputs. The converters achieve high efficiency at the system level by switching simultaneously to avoid charge-sharing losses and by using an adaptive clock to maximize performance for the resulting voltage ripple. Details about the implementation of the DC-DC switches, DC-DC controller, and adaptive clock are provided, and the sources of conversion loss are analyzed based on measured results. This system pushes the capabilities of dynamic voltage scaling by enabling fast transitions (20 ns), simple packaging (no off-chip passives), low area overhead (16%), high conversion efficiency (80%-86%), and high energy efficiency (26.2 DP GFLOPS/W) for mobile devices

The Study of the Pioneer Anomaly: New Data and Objectives for New Investigation

Radiometric tracking data from Pioneer 10 and 11 spacecraft has consistently indicated the presence of a small, anomalous, Doppler frequency drift, uniformly changing with a rate of ~6 x 10^{-9} Hz/s; the drift can be interpreted as a constant sunward acceleration of each particular spacecraft of a_P = (8.74 \pm 1.33) x 10^{-10} m/s^2. This signal is known as the Pioneer anomaly; the nature of this anomaly remains unexplained. We discuss the efforts to retrieve the entire data sets of the Pioneer 10/11 radiometric Doppler data. We also report on the recently recovered telemetry files that may be used to reconstruct the engineering history of both spacecraft using original project documentation and newly developed software tools. We discuss possible ways to further investigate the discovered effect using these telemetry files in conjunction with the analysis of the much extended Doppler data. We present the main objectives of new upcoming study of the Pioneer anomaly, namely i) analysis of the early data that could yield the direction of the anomaly, ii) analysis of planetary encounters, that should tell more about the onset of the anomaly, iii) analysis of the entire dataset, to better determine the anomaly's temporal behavior, iv) comparative analysis of individual anomalous accelerations for the two Pioneers, v) the detailed study of on-board systematics, and vi) development of a thermal-electric-dynamical model using on-board telemetry. The outlined strategy may allow for a higher accuracy solution for a_P and, possibly, will lead to an unambiguous determination of the origin of the Pioneer anomaly.Comment: 43 pages, 40 figures, 3 tables, minor changes before publicatio