Design and performance analysis of human body communication digital transceiver for wireless body area network applications

Wireless body area network (WBAN) is a prominent technology for resolving health-care concerns and providing high-speed continuous monitoring and real-time help. Human body communication (HBC) is an IEEE 802.15.6 physical layer standard for short-range communications that is not reliant on radio frequency (RF). Most WBAN applications can benefit from the HBC's low-latency and low-power architectural features. In this manuscript, an efficient digital HBC transceiver (TR) hardware architecture is designed as per IEEE 802.15.6 standard to overcome the drawbacks of the RF-wireless communication standards like signal leakage, on body antenna and power consumption. The design is created using a frequency selective digital transmission scheme for transmitter and receiver modules. The design resources are analyzed using different field programmable gate array (FPGA) families. The HBC TR utilizes <1% slices, consumes 101 mW power, and provides a throughput of 24.31 Mbps on Artix-7 FPGA with a latency of 10.5 clock cycles. In addition, the less than 10-4bit error rate of HBC is achieved with a 9.52 Mbps data rate. The proposed work is compared with existing architectures with significant improvement in performance parameters like chip area, power, and data rate

Performance evaluation of wake-up radio based wireless body area network

Abstract. The last decade has been really ambitious in new research and development techniques to reduce energy consumption especially in wireless sensor networks (WSNs). Sensor nodes are usually battery-powered and thus have very limited lifetime. Energy efficiency has been the most important aspect to discuss when talking about wireless body area network (WBAN) in particular, since it is the bottleneck of these networks. Medium access control (MAC) protocols hold the vital position to determine the energy efficiency of a WBAN, which is a key design issue for battery operated sensor nodes. The wake-up radio (WUR) based MAC and physical layer (PHY) have been evaluated in this research work in order to contribute to the energy efficient solutions development. WUR is an on-demand approach in which the node is woken up by the wake-up signal (WUS). A WUS switches a node from sleep mode to wake up mode to start signal transmission and reception. The WUS is transmitted or received by a secondary radio transceiver, which operates on very low power. The energy benefit of using WUR is compared with conventional duty-cycling approach. As the protocol defines the nodes in WUR based network do not waste energy on idle listening and are only awakened when there is a request for communication, therefore, energy consumption is extremely low. The performance of WUR based MAC protocol has been evaluated for both physical layer (PHY) and MAC for transmission of WUS and data. The probabilities of miss detection, false alarm and detection error rates are calculated for PHY and the probabilities of collision and successful data transmission for channel access method Aloha is evaluated. The results are obtained to compute and compare the total energy consumption of WUR based network with duty cycling. The results prove that the WUR based networks have significant potential to improve energy efficiency, in comparison to conventional duty cycling approach especially, in the case of low data-reporting rate applications. The duty cycle approach is better than WUR approach when sufficiently low duty cycle is combined with highly frequent communication between the network nodes

RF Integrated Circuits for Energy Autonomous Sensor Nodes.

The exponential growth in the semiconductor industry has enabled computers to pervade our everyday lives, and as we move forward many of these computers will have form factors much smaller than a typical laptop or smartphone. Sensor nodes will soon be deployed ubiquitously, capable of capturing information of their surrounding environment. The next step is to connect all these different nodes together into an entire interconnected system. This “Internet of Things” (IoT) vision has incredible potential to change our lives commercially, societally, and personally. The backbone of IoT is the wireless sensor node, many of which will operate under very rigorous energy constraints with small batteries or no batteries at all. It has been shown that in sensor nodes, radio communication is one of the biggest bottlenecks to ultra-low power design. This research explores ways to reduce energy consumption in radios for wireless sensor networks, allowing them to run off harvested energy, while maintaining qualities that will allow them to function in a real world, multi-user environment. Three different prototypes have been designed demonstrating these techniques. The first is a sensitivity-reduced nanowatt wake-up radio which allows a sensor node to actively listen for packets even when the rest of the node is asleep. CDMA codes and interference rejection reduce the potential for energy-costly false wake-ups. The second prototype is a full transceiver for a body-worn EKG sensor node. This transceiver is designed to have low instantaneous power and is able to receive 802.15.6 Wireless Body Area Network compliant packets. It uses asymmetric communication including a wake-up receiver based on the previous design, UWB transmitter and a communication receiver. The communication receiver has 10 physical channels to avoid interference and demodulates coherent packets which is uncommon for low power radios, but dictated by the 802.15.6 standard. The third prototype is a long range transceiver capable of >1km communication range in the 433MHz band and able to interface with an existing commercial radio. A digitally assisted baseband demodulator was designed which enables the ability to perform bit-level as well as packet-level duty cycling which increases the radio's energy efficiency.PhDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/110432/1/nerobert_1.pd

Millimeter-Scale and Energy-Efficient RF Wireless System

This dissertation focuses on energy-efficient RF wireless system with millimeter-scale dimension, expanding the potential use cases of millimeter-scale computing devices. It is challenging to develop RF wireless system in such constrained space. First, millimeter-sized antennae are electrically-small, resulting in low antenna efficiency. Second, their energy source is very limited due to the small battery and/or energy harvester. Third, it is required to eliminate most or all off-chip devices to further reduce system dimension. In this dissertation, these challenges are explored and analyzed, and new methods are proposed to solve them. Three prototype RF systems were implemented for demonstration and verification. The first prototype is a 10 cubic-mm inductive-coupled radio system that can be implanted through a syringe, aimed at healthcare applications with constrained space. The second prototype is a 3x3x3 mm far-field 915MHz radio system with 20-meter NLOS range in indoor environment. The third prototype is a low-power BLE transmitter using 3.5x3.5 mm planar loop antenna, enabling millimeter-scale sensors to connect with ubiquitous IoT BLE-compliant devices. The work presented in this dissertation improves use cases of millimeter-scale computers by presenting new methods for improving energy efficiency of wireless radio system with extremely small dimensions. The impact is significant in the age of IoT when everything will be connected in daily life.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/147686/1/yaoshi_1.pd

Passive Mixer-based UWB Receiver with Low Loss, High Linearity and Noise-cancelling for Medical Applications

A double balanced passive mixer-based receiver operating in the 3-5 GHz UWB for medical applications is described in this paper. The receiver front-end circuit is composed of an inductorless low noise amplifier (LNA) followed by a fully differential voltage-driven double-balanced passive mixer. A duty cycle of 25% was chosen to eliminate overlap between LO signals, thereby improving receiver linearity. The LNA realizes a gain of 25.3 dB and a noise figure of 2.9 dB. The proposed receiver achieves an IIP3 of 3.14 dBm, an IIP2 of 17.5 dBm and an input return loss (S11) below -12.5dB. Designed in 0.18μm CMOS technology, the proposed mixer consumes 0.72pW from a 1.8V power supply. The designed receiver demonstrated a good ports isolation performance with LO_IF isolation of 60dB and RF_IF isolation of 78dB

Designing Flexible, Energy Efficient and Secure Wireless Solutions for the Internet of Things

The Internet of Things (IoT) is an emerging concept where ubiquitous physical objects (things) consisting of sensor, transceiver, processing hardware and software are interconnected via the Internet. The information collected by individual IoT nodes is shared among other often heterogeneous devices and over the Internet. This dissertation presents flexible, energy efficient and secure wireless solutions in the IoT application domain. System design and architecture designs are discussed envisioning a near-future world where wireless communication among heterogeneous IoT devices are seamlessly enabled. Firstly, an energy-autonomous wireless communication system for ultra-small, ultra-low power IoT platforms is presented. To achieve orders of magnitude energy efficiency improvement, a comprehensive system-level framework that jointly optimizes various system parameters is developed. A new synchronization protocol and modulation schemes are specified for energy-scarce ultra-small IoT nodes. The dynamic link adaptation is proposed to guarantee the ultra-small node to always operate in the most energy efficiency mode, given an operating scenario. The outcome is a truly energy-optimized wireless communication system to enable various new applications such as implanted smart-dust devices. Secondly, a configurable Software Defined Radio (SDR) baseband processor is designed and shown to be an efficient platform on which to execute several IoT wireless standards. It is a custom SIMD execution model coupled with a scalar unit and several architectural optimizations: streaming registers, variable bitwidth, dedicated ALUs, and an optimized reduction network. Voltage scaling and clock gating are employed to further reduce the power, with a more than a 100% time margin reserved for reliable operation in the near-threshold region. Two upper bound systems are evaluated. A comprehensive power/area estimation indicates that the overhead of realizing SDR flexibility is insignificant. The benefit of baseband SDR is quantified and evaluated. To further augment the benefits of a flexible baseband solution and to address the security issue of IoT connectivity, a light-weight Galois Field (GF) processor is proposed. This processor enables both energy-efficient block coding and symmetric/asymmetric cryptography kernel processing for a wide range of GF sizes (2^m, m = 2, 3, ..., 233) and arbitrary irreducible polynomials. Program directed connections among primitive GF arithmetic units enable dynamically configured parallelism to efficiently perform either four-way SIMD GF operations, including multiplicative inverse, or a long bit-width GF product in a single cycle. This demonstrates the feasibility of a unified architecture to enable error correction coding flexibility and secure wireless communication in the low power IoT domain.PHDComputer Science & EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/137164/1/yajchen_1.pd

A 3.1-4.8GHz IR-UWB All-Digital Pulse Generator in 0.13-um CMOS Technology for WBAN Systems

Analog, Digital & RF Circuit DesignImpulse Radio Ultra-WideBand (IR-UWB) systems have drawn growing attention for wireless sensor networks such as Wireless Personal Area Network (WPAN) and Wireless Body Area Network (WBAN) systems ever since the Federal Communications Commission (FCC) released the spectrum between 3.1 and 10.6GHz for unlicensed use in 2002. The restriction on transmitted power spectral density in this band is equal to the noise emission limit of household digital electronics. This band is also shared with several existing service, therefore in-band interference is expected and presents a challenge to UWB system design. UWB devices as secondary spectrum users must also detect and avoid (DAA) other licensed users from the cognitive radio???s point of view. For the DAA requirement, it is more effective to deploy signal with variable center frequency and a minimum 10dB bandwidth of 500MHz than a signal covering the entire UWB spectrum range with fixed center frequency. A key requirement of the applications using IR-UWB signal is ultra-low power consumption for longer battery life. Also, cost reduction is highly desirable. Recently, digital IR-UWB pulse generation is studied more than analog approach due to its lower power consumption. An all-digital pulse generator in a standard 0.13-um CMOS technology for communication systems using Impulse Radio Ultra-WideBand (IR-UWB) signal is presented. A delay line-based architecture utilizing only static logic gates and leading lower power consumption for pulse generation is proposed in this thesis. By using of all-digital architecture, energy is consumed by CV2 switching losses and sub-threshold leakage currents, without RF oscillator or analog bias currents. The center frequency and the fixed bandwidth of 500MHz of the output signal can be digitally controlled to cover three channels in low band of UWB spectrum. Delay based Binary Shift Keying (DB-BPSK) and Pulse Position Modulation (PPM) schemes are exploited at the same time to modulate the transmitted signals with further improvement in spectrum characteristics. The total energy consumption is 48pJ/pulse at 1.2V supply voltage, which is well suitable for WBAN systems.ope

An efficient ultra-wideband digital transceiver for wireless applications on the field-programmable gate array platform

The ultra-wideband (UWB) technology is a promising short-range communication technology for most wireless applications. The UWB works at higher frequencies and is affected by interferences with the same frequency standards. This manuscript has designed an efficient and low-cost implementation of IEEE 802.15.4a-based UWB-digital transceiver (DTR). The design module contains UWB transmitter (TX), channel, and UWB-receiver (RX) units. Convolutional encoding and modulation units like burst position modulation and binary phase-shift keying modulation are used to construct the UWB-TX. The synchronization and Viterbi decoder units are used to recover the original data bits and are affected by noise in UWB-RX. The UWB-DTR is synthesized using Xilinx ISE® environment with Verilog hardware description language (HDL) and implemented on Artix-7 field-programmable gate array (FPGA). The UWB-DTR utilizes less than 2% (slices and look-up table/LUTs), operates at 268 MHz, and consumes 91 mW of total power on FPGA. The transceiver achieves a 6.86 Mbps data rate, which meets the IEEE 802.15.4a standard. The UWB-DTR module obtains the bit error rate (BER) of 2×10-4 by transmitting 105 data bits. The UWB-DTR module is compared with similar physical layer (PHY) transceivers with improvements in chip area (slices), power, data rate, and BER. 

Design of an efficient binary phase-shift keying based IEEE 802.15.4 transceiver architecture and its performance analysis

The IEEE 802.15.4 physical layer (PHY) standard is one of the communication standards with wireless features by providing low-power and low-data rates in wireless personal area network (WPAN) applications. In this paper, an efficient IEEE 802.15.4 digital transceiver hardware architecture is designed using the binary phase-shift keying (BPSK) technique. The transceiver mainly has transmitter and receiver modules along with the error calculation unit. The BPSK modulation and demodulation are designed using a digital frequency synthesizer (DFS). The DFS is used to generate the in-phase (I) and quadrature-phase (Q) signals and also provides better system performance than the conventional voltage-controlled oscillator (VCO) and look up table (LUT) based memory methods. The differential encoding-decoding mechanism is incorporated to recover the bits effectively and to reduce the hardware complexity. The simulation results are illustrated and used to find the error bits. The design utilizes less chip area, works at 268.2 MHz, and consumes 108 mW of total power. The IEEE 802.15.4 transceiver provides a latency of 3.5 clock cycles and works with a throughput of 76.62 Mbps. The bit error rate (BER) of 2×10-5 is achieved by the proposed digital transceiver and is suitable for real-time applications. The work is compared with existing similar approaches with better improvement in performance parameters