Design of an RC Oscillator for Automotive Applications

Tato práce je zaměřena na návrh integrovaného relaxačního oscilátoru pro automobilové aplikace, které jsou charakteristické extrémními provozními podmínkami a vysokými požadavky na robustnost. Z dostupné literatury byla provedena rešerše, která umožnila postihnout nezbytný teoretický základ pro komparativní studii nedávno představených designů integrovaných oscilátorů a také pomohla navrhnout architekturu oscilátoru, která v implementaci zahrnuje princip IEF. Za účelem předpovězení negativních vlivů na výkon systému a optimálních parametrů bloků byly provedeny simulace vysokoúrovňového modelu. V práci je diskutována implementace jednotlivých bloků a prezentovány výsledky simulace kritických parametrů. Simulace navrženého oscilátoru prokázaly konzistenci konceptu IEF pro praktickou realizaci. Realizovaný systém však potřebuje další vylepšení.The thesis is aimed on the integrated relaxation oscillator design for automotive applications, that are characterized by harsh operation conditions and high robustness requirements. Literature research was conducted to acquire necessary theoretical basis for comparative study of the recently proposed integrated oscillator designs to choose the oscillator architecture utilizing integrated-error feedback for the implementation. High-level model simulations were conducted to predict negative influences on the system performance and to suggest blocks optimal parameters for the design. The implementation of the designed blocks was discussed, and simulation results of the critical parameters were presented. The designed oscillator simulations proved the consistency of the integrated-error feedback concept for practical realization. However, the designed system needs further improvements

Ultra-Low-Power Sensors and Receivers for IoT Applications

The combination of ultra-low power analog front-ends and CMOS-compatible transducers enable new applications, such as environmental monitors, household appliances, health trackers, etc. that are seamlessly integrated into our daily lives. Furthermore, wireless connectivity allows many of these sensors to operate both independently and collectively. These techniques collectively fulfil the recent surge of internet-of-things (IoT) applications that have the potential to fundamentally change daily life for millions of people.In this dissertation, the circuit and system design of wireless receivers and sensors is presented that explores the challenges of implementing long lifespan, high accuracy, and large coverage range IoT sensor networks. The first is a wake-up receiver (WuRX), which continuously monitors the RF environment to wake up a higher-power radio upon detection of a predetermined RF signature. This work both improves sensitivity and reduces power over prior art through a multi-faceted design featuring an impedance transformation network with large passive voltage gain, an active envelope detector with high input impedance to facilitate large passive voltage gain, a low-power precision comparator, and a low-leakage digital baseband correlator.Although pushing the prior WuRX performance boundary by orders of magnitude, the first work shows moderate sensitivity, inferior temperature robustness, and large area with external lumped components. Thus, the second work shows a miniaturized WuRX that is temperature-compensated, yet still consumes only nano-watt power and millimeter area while operating at 9 GHz. To further reduce the area, a global common-mode feedback is utilized across the envelope detector and baseband amplifier that eliminates the need for off-chip ac-coupling components. Multiple temperature-compensation techniques are proposed to maintain constant bandwidth of the signal path and constant clock frequency. Both WuRXs operate at 0.4 V supply, consume near-zero power and achieve ~-70 dBm sensitivity.Lastly, the first reported CMOS 2-in-1 relative humidity and temperature sensor is presented. A unified analog front-end interfaces on-chip transducers and converts the inputs into a frequency vis a high-linearity frequency-locked loop. An incomplete-settling switched-capacitor-based Wheatstone bridge is proposed to sense the inputs in a power-efficient fashion

A 120nW 18.5kHz RC oscillator with comparator offset cancellation for ±0.25% temperature stability

Integrated low-frequency oscillators can replace crystal oscillators as sleep-mode timers to reduce the size and cost of wireless sensors [1]. Since the timer is one of the few continuously functioning circuits, minimizing its power consumption can greatly reduce sleep-mode power of highly duty-cycled systems. Temperature stability of the oscillator is important in order to minimize timing uncertainly and guard time for the radios, and thus maximizing sleep time. The voltage-averaging feedback method described in [2] achieves high stability in the MHz frequencies, but when scaled to the kHz range, requires very large filters. On the other extreme, gate leakage-based timers have been designed for sub-nW power consumption, but operate in the sub-Hz frequencies [3]. In the past, high accuracy RC oscillators in the kHz range have been designed with feed-forward correction [1] and self-chopped operation [4]. In this work, an offset cancellation architecture achieves long-term frequency stability and temperature stability while operating at lower power

A Flexible, Highly Integrated, Low Power pH Readout

Medical devices are widely employed in everyday life as wearable and implantable technologies make more and more technological breakthroughs. Implantable biosensors can be implanted into the human body for monitoring of relevant physiological parameters, such as pH value, glucose, lactate, CO2 [carbon dioxide], etc. For these applications the implantable unit needs a whole functional set of blocks such as micro- or nano-sensors, sensor signal processing and data generation units, wireless data transmitters etc., which require a well-designed implantable unit.Microelectronics technology with biosensors has caused more and more interest from both academic and industrial areas. With the advancement of microelectronics and microfabrication, it makes possible to fabricate a complete solution on an integrated chip with miniaturized size and low power consumption.This work presents a monolithic pH measurement system with power conditioning system for supply power derived from harvested energy. The proposed system includes a low-power, high linearity pH readout circuits with wide pH values (0-14) and a power conditioning unit based on low drop-out (LDO) voltage regulator. The readout circuit provides square-wave output with frequency being highly linear corresponding to the input pH values. To overcome the process variations, a simple calibration method is employed in the design which makes the output frequency stay constant over process, supply voltage and temperature variations. The prototype circuit is designed and fabricated in a standard 0.13-μm [micro-meter] CMOS process and shows good linearity to cover the entire pH value range from 0-14 while the voltage regulator provides a stable supply voltage for the system

A 28 nm 368 fJ/cycle, 0.43%/V Supply Sensitivity, FLL based RC Oscillator Featuring Positive TC Only Resistors and ΣM Based Trimming

This Brief presents a process-scaling-friendly frequency-locked-loop (FLL)-based RC oscillator. It features an R-R-C frequency-to-voltage converter that entails resistors with only the same-sign temperature coefficients. Together with a low-leakage switched-capacitor resistor and a delta-sigma-modulator-based trimming, our 71.8-MHz RC oscillator in 28-nm CMOS achieves a frequency inaccuracy of 77.6 ppm/0C, a 0.43%/V supply sensitivity, and an 11-psrms period jitter. The energy efficiency is 368 fJ/cycle

Noise shaping Asynchronous SAR ADC based time to digital converter

Time-to-digital converters (TDCs) are key elements for the digitization of timing information in modern mixed-signal circuits such as digital PLLs, DLLs, ADCs, and on-chip jitter-monitoring circuits. Especially, high-resolution TDCs are increasingly employed in on-chip timing tests, such as jitter and clock skew measurements, as advanced fabrication technologies allow fine on-chip time resolutions. Its main purpose is to quantize the time interval of a pulse signal or the time interval between the rising edges of two clock signals. Similarly to ADCs, the performance of TDCs are also primarily characterized by Resolution, Sampling Rate, FOM, SNDR, Dynamic Range and DNL/INL. This work proposes and demonstrates 2nd order noise shaping Asynchronous SAR ADC based TDC architecture with highest resolution of 0.25 ps among current state of art designs with respect to post-layout simulation results. This circuit is a combination of low power/High Resolution 2nd Order Noise Shaped Asynchronous SAR ADC backend with simple Time to Amplitude converter (TAC) front-end and is implemented in 40nm CMOS technology. Additionally, special emphasis is given on the discussion on various current state of art TDC architectures.Electrical and Computer Engineerin

Low jitter design techniques for monolithic CMOS phase-locked and delay-locked systems

Timing jitter is a major concern in almost every type of communication system. Yet the desire for high levels of integration works against minimization of this error, especially for systems employing a phase-locked loop (PLL) or delay-locked loop (DLL) for timing generation or timing recovery. There has been an increasing demand for fully-monolithic CMOS PLL and DLL designs with good jitter performance. In this thesis, the system level as well as the transistor level low jitter design techniques for integrated PLLs and DLLs have been explored.;On the system level, a rigorous jitter analysis method based on a z-domain model is developed, in which the jitter is treated as a random event. Combined with statistical methods, the rms value of the accumulated jitter can be expressed with a closed form solution that successfully ties the jitter performance with loop parameters. Based on this analysis, a cascaded PLL/DLL structure is proposed which combines the advantage of both loops. The resulting system is able to perform frequency synthesis with the jitter as low as that of a DLL.;As an efficient tool to predict the jitter performance of a PLL or DLL system, a new nonlinear behavioral simulator is developed based on a novel behavioral modeling of the VCO and delay-line. Compared with prior art, this simulator not only simplifies the computation but also enables the noise simulation. Both jitter performance during tracking and lock condition can be predicted. This is also the first reported top-level simulation tool for DLL noise simulation.;On the transistor level, three prototype chips for different applications were implemented and tested. The first two chips are the application of PLL in Gigabit fibre channel transceivers. High speed circuit blocks that have good noise immunity are the major design concern. Testing results show that both designs have met the specifications with low power dissipation. For the third chip, an adaptive on-chip dynamic skew calibration technique is proposed to realize a precise delay multi-phase clock generator, which is a topic that has not been addressed in previous work thus far. Experimental results strongly support the effectiveness of the calibration scheme. At the same time, this design achieves by far the best reported jitter performance

Multi-Loop-Ring-Oscillator Design and Analysis for Sub-Micron CMOS

Ring oscillators provide a central role in timing circuits for today?s mobile devices and desktop computers. Increased integration in these devices exacerbates switching noise on the supply, necessitating improved supply resilience. Furthermore, reduced voltage headroom in submicron technologies limits the number of stacked transistors available in a delay cell. Hence, conventional single-loop oscillators offer relatively few design options to achieve desired specifications, such as supply rejection. Existing state-of-the-art supply-rejection- enhancement methods include actively regulating the supply with an LDO, employing a fully differential or current-starved delay cell, using a hi-Z voltage-to-current converter, or compensating/calibrating the delay cell. Multiloop ring oscillators (MROs) offer an additional solution because by employing a more complex ring-connection structure and associated delay cell, the designer obtains an additional degree of freedom to meet the desired specifications. Designing these more complex multiloop structures to start reliably and achieve the desired performance requires a systematic analysis procedure, which we attack on two fronts: (1) a generalized delay-cell viewpoint of the MRO structure to assist in both analysis and circuit layout, and (2) a survey of phase-noise analysis to provide a bank of methods to analyze MRO phase noise. We distill the salient phase-noise-analysis concepts/key equations previously developed to facilitate MRO and other non-conventional oscillator analysis. Furthermore, our proposed analysis framework demonstrates that all these methods boil down to obtaining three things: (1) noise modulation function (NMF), (2) noise transfer function (NTF), and (3) current-controlled-oscillator gain (KICO). As a case study, we detail the design, analysis, and measurement of a proposed multiloop ring oscillator structure that provides improved power-supply isolation (more than 20dB increase in supply rejection over a conventional-oscillator control case fabricated on the same test chip). Applying our general multi-loop-oscillator framework to this proposed MRO circuit leads both to design-oriented expressions for the oscillation frequency and supply rejection as well as to an efficient layout technique facilitating cross-coupling for improved quadrature accuracy and systematic, substantially simplified layout effort

Low-Power Energy Efficient Circuit Techniques for Small IoT Systems

Although the improvement in circuit speed has been limited in recent years, there has been increased focus on the internet of things (IoT) as technology scaling has decreased circuit size, power usage and cost. This trend has led to the development of many small sensor systems with affordable costs and diverse functions, offering people convenient connection with and control over their surroundings. This dissertation discusses the major challenges and their solutions in realizing small IoT systems, focusing on non-digital blocks, such as power converters and analog sensing blocks, which have difficulty in following the traditional scaling trends of digital circuits. To accommodate the limited energy storage and harvesting capacity of small IoT systems, this dissertation presents an energy harvester and voltage regulators with low quiescent power and good efficiency in ultra-low power ranges. Switched-capacitor-based converters with wide-range energy-efficient voltage-controlled oscillators assisted by power-efficient self-oscillating voltage doublers and new cascaded converter topologies for more conversion ratio configurability achieve efficient power conversion down to several nanowatts. To further improve the power efficiency of these systems, analog circuits essential to most wireless IoT systems are also discussed and improved. A capacitance-to-digital sensor interface and a clocked comparator design are improved by their digital-like implementation and operation in phase and frequency domain. Thanks to the removal of large passive elements and complex analog blocks, both designs achieve excellent area reduction while maintaining state-of-art energy efficiencies. Finally, a technique for removing dynamic voltage and temperature variations is presented as smaller circuits in advanced technologies are more vulnerable to these variations. A 2-D simultaneous feedback control using an on-chip oven control locks the supply voltage and temperature of a small on-chip domain and protects circuits in this locked domain from external voltage and temperature changes, demonstrating 0.0066 V/V and 0.013 °C/°C sensitivities to external changes. Simple digital implementation of the sensors and most parts of the control loops allows robust operation within wide voltage and temperature ranges.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/138743/1/wanyeong_1.pd

Design techniques for temperature insensitive, low phase noise oscillator

A reference clock generator is one of the most important components in many electronic devices. Common clock references are based on quartz crystals which offer high quality factor, good phase noise performance and excellent stability against temperature, voltage and process variation. However, due to incompatibility with silicon integration and high power consumption, they are not suitable for biomedical devices which require long battery lifetime, low cost and especially small size but do not require near-crystal accuracy. This thesis focuses on eliminating the quartz crystals and generating reference clock on a silicon chip. Moreover, this thesis proposes a way of combining two major oscillator types available in CMOS (RC and Ring) technology, while preserving the unique qualities of both of them and coming up with the proposed RCR (resistor-capacitor-ring) oscillator, that o ffers an excellent alternative for biomedical devices and wireless sensor networks. We coin the term RCR signifying the proposed approach of combining RC oscillators with ring oscillators to achieve a performance better than the performance of individual RC and ring oscillators. In order to generate stable clock frequency against temperature and supply variations a novel CMOS reference clock oscillator is proposed which exploits the RC and ring oscillator performances, providing the best of both worlds in performance. The proposed oscillator employs a supply-regulated ring oscillator in a feedback loop that follows a frequency insensitive RC oscillator, which minimizes the frequency sensitivity to supply and temperature variations. The clock oscillator achieves negligible frequency variation against supply variation of 1.1 V to 1.3 V and 0:37% against temperature variation of -40 C 125 C. In addition, low power consumption is achieved by using mostly digital circuitry operating at very low frequencies. Even the phase noise performance of the proposed oscillator shows a very high FoM of about 160 dB at the o set frequencies of 100 kHz and 1 MHz. This stability to temperature and supply along with excellent noise performance is the unique cornerstone of RCR oscillators proposed in this thesis, which cannot be found in any full-CMOS oscillators. When the performance of the clock oscillator is compared to that of the recently reported low power CMOS reference clock oscillators, the frequency variation to supply variation is reduced to zero, temperature sensitivity is also improved by approximately a factor of 3 and normalized power consumption to frequency output is reduced by a factor of 5. The proposed CMOS clock oscillator is implemented in 65 nm TSMC CMOS technology and consumes just 220 W from 1.2 V supply at an output frequency of 50 MHz