Simulator for heterogeneous dataflow architectures

A new simulator is developed to simulate the execution of an algorithm graph in accordance with the Algorithm to Architecture Mapping Model (ATAMM) rules. ATAMM is a Petri Net model which describes the periodic execution of large-grained, data-independent dataflow graphs and which provides predictable steady state time-optimized performance. This simulator extends the ATAMM simulation capability from a heterogenous set of resources, or functional units, to a more general heterogenous architecture. Simulation test cases show that the simulator accurately executes the ATAMM rules for both a heterogenous architecture and a homogenous architecture, which is the special case for only one processor type. The simulator forms one tool in an ATAMM Integrated Environment which contains other tools for graph entry, graph modification for performance optimization, and playback of simulations for analysis

Efficient Simulation of Structural Faults for the Reliability Evaluation at System-Level

In recent technology nodes, reliability is considered a part of the standard design ¿ow at all levels of embedded system design. While techniques that use only low-level models at gate- and register transfer-level offer high accuracy, they are too inefficient to consider the overall application of the embedded system. Multi-level models with high abstraction are essential to efficiently evaluate the impact of physical defects on the system. This paper provides a methodology that leverages state-of-the-art techniques for efficient fault simulation of structural faults together with transaction-level modeling. This way it is possible to accurately evaluate the impact of the faults on the entire hardware/software system. A case study of a system consisting of hardware and software for image compression and data encryption is presented and the method is compared to a standard gate/RT mixed-level approac

Advanced flight deck/crew station simulator functional requirements

This report documents a study of flight deck/crew system research facility requirements for investigating issues involved with developing systems, and procedures for interfacing transport aircraft with air traffic control systems planned for 1985 to 2000. Crew system needs of NASA, the U.S. Air Force, and industry were investigated and reported. A matrix of these is included, as are recommended functional requirements and design criteria for simulation facilities in which to conduct this research. Methods of exploiting the commonality and similarity in facilities are identified, and plans for exploiting this in order to reduce implementation costs and allow efficient transfer of experiments from one facility to another are presented

A design tool for high-resolution high-frequency cascade continuous- time Σ∆ modulators

Event: Microtechnologies for the New Millennium, 2007, Maspalomas, Gran Canaria, SpainThis paper introduces a CAD methodology to assist the de signer in the implementation of continuous-time (CT) cas- cade Σ∆ modulators. The salient features of this methodology ar e: (a) flexible behavioral modeling for optimum accuracy- efficiency trade-offs at different stages of the top-down synthesis process; (b) direct synthesis in the continuous-time domain for minimum circuit complexity and sensitivity; a nd (c) mixed knowledge-based and optimization-based architec- tural exploration and specification transmission for enhanced circuit performance. The applicability of this methodology will be illustrated via the design of a 12 bit 20 MHz CT Σ∆ modulator in a 1.2V 130nm CMOS technology.Ministerio de Ciencia y Educación TEC2004-01752/MICMinisterio de Industria, Turismo y Comercio FIT-330100-2006-134 SPIRIT Projec

Simulator verification techniques study. Integrated simulator self test system concepts

Software and hardware requirements for implementing hardware self tests are presented in support of the development of training and procedures development simulators for the space shuttle program. Self test techniques for simulation hardware and the validation of simulation performance are stipulated. The requirements of an integrated simulator self system are analyzed. Readiness tests, fault isolation tests, and incipient fault detection tests are covered

Creative use of BIPV materials: barriers and solutions

Inventive use of photovoltaic (PV) materials in architecture can be developed through use of PV in artworks. This is particularly important in increasing the uptake of building-integrated building-integrated photovoltaics (BIPV), by developing novel methods of combining and installing PV materials. Current examples of PV artwork and design are examined, from small to large scale, to assess the current design limitations. The design of two PV artworks is discussed in detail, including an artwork that uses the principle of the luminescent solar concentrator (LSC), to show the way in which design hurdles are discovered and overcome. Challenges range from difficulties in obtaining small quantities of PV materials; the balance between efficiency and artistic effect; through to technical and siting issues that an artist must address when designing a functional PV structure. Methods of overcoming these barriers are explored, including the use of lumogen dyes in encapsulant materials