Study of Novel Power Semiconductor Devices for Performance and Reliability.

Power Semiconductor Devices are crucial components in present day power electronic systems. The performance and efficiency of the devices have a direct correlation with the power system efficiency. This dissertation will examine some of the components that are commonly used in a power system, with emphasis on their performance characteristics and reliability. In recent times, there has a proliferation of charge balance devices in high voltage discrete power devices. We examine the same charge balance concept in a fast recovery diode and a MOSFET. This is crucial in the extending system performance at compact dimensions. At smaller device and system sizes, the performance trade-off between the ON and OFF states becomes all the more critical. The focus on reducing the switching losses while maintaining system reliability increases. In a conventional planar technology, the technology places a limit on the switching performance owing to the larger die sizes. Using a charge balance structure helps achieve the improved trade-off, while working towards ultimately improving system reliability, size and cost. Chapter 1 introduces the basic power system based on an inductive switching circuit, and the various components that determine its efficiency. Chapter 2 presents a novel Trench Fast Recovery Diode (FRD) structure with injection control is proposed in this dissertation. The proposed structure achieves improved carrier profile without the need for excess lifetime control. This substantially improves the device performance, especially at extreme temperatures (-40oC to 175oC). The device maintains low leakage at high temperatures, and it\u27s Qrr and Irm do not degrade as is the usual case in heavily electron radiated devices. A 1600 diode using this structure has been developed, with a low forward turn-on voltage and good reverse recovery properties. The experimental results show that the structure maintains its performance at high temperatures. In chapter 3, we develop a termination scheme for the previously mentioned diode. A major limitation on the performance of high voltage power semiconductor is the edge termination of the device. It is critical to maintain the breakdown voltage of the device without compromising the reliability of the device by controlling the surface electric field. A good termination structure is critical to the reliability of the power semiconductor device. The proposed termination uses a novel trench MOS with buried guard ring structure to completely eliminate high surface electric field in the silicon region of the termination. The termination scheme was applied towards a 1350 V fast recovery diode, and showed excellent results. It achieved 98% of parallel plane breakdown voltage, with low leakage and no shifts after High Temperature Reverse Bias testing due to mobile ion contamination from packaging mold compound. In chapter 4, we also investigate the device physics behind a superjunction MOSFET structure for improved robustness. The biggest issue with a completely charge balanced MOSFET is decreased robustness in an Unclamped Inductive Switching (UIS) Circuit. The equally charged P and N pillars result in a flat electric field profile, with the peak carrier density closer to the P-N junction at the surface. This results in an almost negligible positive dynamic Rds-on effect in the MOSFET. By changing the charge profile of the P-column, either by increasing it completely or by implementing a graded profile with the heavier P on top, we can change the field profile and shift the carrier density deeper into silicon, increasing the positive dynamic Rds-on effect. Simulation and experimental results are presented to support the theory and understanding. Chapter 5 summarizes all the theories presented and the contributions made by them in the field. It also seeks to highlight future work to be done in these areas

Oxide bypassed power MOSFET devices

Master'sMASTER OF ENGINEERIN

Design, simulation and fabrication of 4H-SiC Power MOSFETs

For a 4H-SiC MOSFET to compete with Si counterparts, especially at lower voltages (1.2kV), the channel resistance contributes to a significant part in the total on-state resistance which must be addressed. Since most of the commercially available SiC wafer materials are grown on the {0001} crystal plane, a trench-gate MOSFET is necessary to take the advantage of the higher reported channel mobility on the {112 ̅ 0} crystal plane. 1.2kV trench MOSFET design and fabrication is the main focus in this work. The micro-trench free dry etching process has first been developed with a systematic study on the dry etching parameters. Trench corner rounding has also been investigated since a rounded corner is normally preferred to avoid an electric field hot spot. Two generations of trench MOSFETs have been designed and fabricated. The 1st generation devices have been used to validate the fabrication process. A maximum breakdown voltage of 1600V has been achieved for the 1st generation devices. The p+ trench bottom shielding region provides the protection for the trench gate oxide since it shifts the peak electric field from the oxide/semiconductor interface to a semiconductor p-n junction; however, it also introduces a parasitic JFET region into the trench MOSFET structure which severely degraded the on-state performance of the 1st generation devices. The 2nd generation devices were designed to eliminate the effect of the parasitic JFET region and improve the on-state performance. The optimised device structure with a current spreading layer (CSL) and p+ implantation clearance in the 2nd generation design has successfully eliminated the effect of the parasitic JFET region. Further design and process optimisation is necessary to increase the current density of the device which was as low as 3A/cm2. A fabrication trial has been carried out on the MOSFETs with integrated Schottky contacts at the termination region and therefore, external Schottky diodes are not necessary for many applications. A 10kV DMOSFET has also been designed and fabricated with maximum breakdown voltage at 13.6kV. The high voltage termination design options have been discussed among the floating field ring (FFR) termination and the junction termination extensions (JTEs). The on-state performance is poor due to a photo mask error on the JFET length which needs to be optimised for the next generation devices. Novel device structures have been studied with simulation. These include trench MOSFET with integrated Schottky diode and 3.3kV superjunction trench MOSFET. The MOSFET with integrated Schottky diode not only reduces the chip area consumption, but also reduces the chip count in the system level. In the proposed design, the Schottky contact is placed at the bottom of the trench structure for the first time. The superjunction structure has a great potential for SiC devices rated at above 3.3kV. The proposed design uses implanted p-pillar with a trench gate structure which combines the benefits of low channel resistance and low drift region resistance

Deep p-Ring Trench Termination: An Innovative and Cost-Effective Way to Reduce Silicon Area

A new type of high voltage termination, namely the “deep p-ring trench” termination design for high voltage, high power devices is presented and extensively simulated. Termination of such devices consumes a large proportion of the chip size; the proposed design concept not only reduces the termination silicon area required, it also removes the need for an additional mask as is the case of the traditional p+ ring type termination. Furthermore, the presence of the p-ring under and around the bottom of the trench structure reduces the electric field peaks at the corners of the oxide which results in reduced hot carrier injection and improved device reliabilit

High Efficiency IGBTs through Novel Three-Dimensional Modelling and New Architectures

New Insulated Gate Bipolar Transistor (IGBT) designs are reliant on simulation tools, such as Sentaurus technology computer-aided design (TCAD) models, which allow for rapid device development that could not be achieved by manufacturing prototypes due to the cost and time associated with fabrication. These simulations are, though, computationally expensive and typically most design engineers develop these TCAD models only in two dimensions. This leads to inaccuracies in the model output since manufactured transistors are inherently three-dimensional (3D). Based upon a commercial IGBT, this thesis begins by outlining the development of a 3D TCAD model using design details provided by the manufacturer. Large variations between the experimental data from the manufactured device and the simulation model lead to the discovery of widespread birds-beaking within the IGBT – an uncontrollable processing defect that the manufacturer was unaware of. This thesis presents a new simulation technique to account for this processing error while minimising computational effort and investigates the consequence of this birds-beak on the reliability of the device. The verified 3D IGBT model was also used to determine an optimum cell design that considered critical 3D effects omitted from previous studies. An extensive literature review for the Reverse-Conducting IGBT (RC-IGBT) is provided. It is shown that despite the benefits of the RC-IGBT, the device suffers from many undesirable design trade-offs that have prevented its widespread use. The RC-IGBT designs that have currently been proposed in literature, either present a trade-off in performance, an inability to be manufactured, or a requirement for a custom gate drive. This thesis presents a new RC-IGBT concept, the ‘Dual Implant SuperJunction (SJ) RC-IGBT’ that addresses these concerns and is manufacturable using current state of the art techniques. The concept and proposed manufacturing method enables, for the first time, a full SuperJunction structure to be achieved in a 1.2kV device. In addition, an investigation into a coordinated switching scheme using both a silicon IGBT and silicon-carbide MOSFET was undertaken, which aimed to improve turn-off losses within the IGBT without sacrificing on-state losses. Thermal modelling of the power devices switching under inductive load was explored as the system was optimised to use a SiC MOSFET in excess of its nominal ratings, reducing the overall system cost.EPSRC Doctoral Training Partnership scheme (grant RG75686

Design and fabrication of superjunction power MOSFET devices

Ph.DDOCTOR OF PHILOSOPH

Design and fabrication of high voltage 4H-SiC Schottky barrier diodes

A novel design of mesa-etch termination and Superjunction JBS diode structure has been proposed and optimized. The new mesa-etch termination can achieve over 90% of ideal maximal breakdown voltage within a wide sidewall implant dose window (~9e16 cm⁻³). Besides the high tolerance on implant dose, the proposed design also exhibits high tolerance on the etch sidewall angle: minimal maximum breakdown voltage was observed with etch sidewall angle variations. The Superjunction JBS diode can obtain both 96.4% maximum super junction breakdown voltage and 76.6% JBS Schottky surface electric field reduction. The super junction maximal breakdown voltage is 1.5 times large as the conventional Schottky diode breakdown voltage and the leakage current is logarithmically related to the surface electric field. The superior breakdown voltage represents a large improvement on the power rectifier performance. Based on these structure improvements, vertical 4H-SiC Schottky Diodes have been fabricated and tested. Vertical 4H-SiC Schottky Diode without any edge termination has a breakdown voltage as large as 692 V and exhibits an on-state specific resistance as small as 7.9 mΩ*cm². Such breakdown voltage is much higher than simulation results. In the meantime, on-state resistance is also much larger than the simulation results. The mechanism for these improved power rectifier performances will be furthered investigated in future studies.Electrical and Computer Engineerin

Introducing the hybrid unipolar bipolar field effect transistor : the HUBFET

Modern commercial aircraft are becoming increasingly dependent on electrical power. More and more of the systems traditionally powered by hydraulics or pneumatics are being migrated to run on electricity. One consequence of the move towards electrical power is the increase in the storage capacity of the bat- teries used to supplement the power generation. The increase in battery size increases the maximum stress that a short circuit failure can put on the power distribution system. Although such failures are extremely rare, the fail safe switches in the distribution system must be capable of handling extremely high energy short circuits and turning off the power to protect the electrical systems from damage. Traditionally aircraft have used electromechanical relays in this role. However, they are large, heavy and slow to switch. As the potential power level is increased, the slow switching becomes more of a problem. The solution is a semiconductor switch. An IGBT can handle the high short circuit currents and switches fast enough to prevent short circuits damaging key systems. However, the inherent voltage drop in the forward current path significantly reduces its efficiency during nominal operation. A power MOSFET would be considerably more efficient than an IGBT during nominal operation. However, during high current surges, the ohmic behaviour of the switch leads to extremely high power loss and thermal failure. In this thesis a solution to this problem is presented. A new class of semiconductor device is proposed that has the highly efficient low current performance of the power MOSFET and the high current handling capability of the IGBT. The device has been named the Hybrid Unipolar Bipolar Field Effect Transistor or HUBFET. The HUBFET operates in unipolar mode, like a MOSFET, at low currents and in bipolar mode, like an IGBT, at high currents. The structure of the HUBFET is a merging of the MOSFET and IGBT. It is a vertical device with a traditional MOS gate structure, however the backside consists of alternating regions of both N-type and P-type doping. Through simulation the key on-state characteristics of the HUBFET have been shown. Fabricated test modules have been tested to validate the simulations and to show how the HUBFET can dynamically transistion from unipolar to bipolar mode during a short circuit event. Following the proof of concept the pattern of implants on the backside of the device that give the HUBFET its characteristic were investigated and potential improvements to the design were identified

MODELLING AND DESIGN OF DIAMOND POWER SEMICONDUCTOR DEVICES

With its remarkable electro-thermal properties such as the highest known thermal conductivity (~22 W/cm∙ K at room temperature) of any material, high hole mobility (>2000 cm2/V∙s), high critical electric field (>10 MV/cm), and large bandgap (5.47 eV), Diamond has overwhelming advantages over Silicon and wide bandgap semiconductors (WBG) for ultra-high voltage and high temperature applications (>3 kV and >450 K, respectively). However, despite its tremendous potential, fabricated devices based on this material have not yet delivered the expected high-performance. This is due to three main reasons: (i) the lack of consistent physical models and design approaches specific to diamond-based devices that could significantly accelerate their development; (ii) the absence of shallow acceptor and donor dopant species which has resulted in poor room temperature performance; (iii) the technological issues of the manufacturing process. With the principal aim of modelling the next generation of diamond devices, this Ph.D dissertation endeavours to numerically model the main electro-thermal properties of diamond devices for power electronic applications. Optimized unipolar mode diamond field effect transistors have been designed by means of finite element simulations and their performance has been assessed against the state-of-the-art diamond FETs. Particular attention is given to the static and dynamic properties of deep dopant levels and their effects in WBG semiconductor-based devices. Moreover, by means of a more global comparison technique and through accurate theoretical analysis, diamond FETs and diodes’ performance have been projected and compared with that of GaN and SiC devices. This work concludes with possible implementations of diamond devices in power converters and provides a roadmap of diamond devices for power electronics. These promising results give a new impetus to the rather small, but growing diamond community and enable future research in the field with the goal of bringing diamond to the commercial world.U.K. Engineering and Physical Sciences Research Council for the University of Cambridge Centre for Doctoral Training under Grant EP/M506485/