CMOS design of chaotic oscillators using state variables: a monolithic Chua's circuit

This paper presents design considerations for monolithic implementation of piecewise-linear (PWL) dynamic systems in CMOS technology. Starting from a review of available CMOS circuit primitives and their respective merits and drawbacks, the paper proposes a synthesis approach for PWL dynamic systems, based on state-variable methods, and identifies the associated analog operators. The GmC approach, combining quasi-linear VCCS's, PWL VCCS's, and capacitors is then explored regarding the implementation of these operators. CMOS basic building blocks for the realization of the quasi-linear VCCS's and PWL VCCS's are presented and applied to design a Chua's circuit IC. The influence of GmC parasitics on the performance of dynamic PWL systems is illustrated through this example. Measured chaotic attractors from a Chua's circuit prototype are given. The prototype has been fabricated in a 2.4- mu m double-poly n-well CMOS technology, and occupies 0.35 mm/sup 2/, with a power consumption of 1.6 mW for a +or-2.5-V symmetric supply. Measurements show bifurcation toward a double-scroll Chua's attractor by changing a bias current

Semiconductor Device Modeling and Simulation for Electronic Circuit Design

This chapter covers different methods of semiconductor device modeling for electronic circuit simulation. It presents a discussion on physics-based analytical modeling approach to predict device operation at specific conditions such as applied bias (e.g., voltages and currents); environment (e.g., temperature, noise); and physical characteristics (e.g., geometry, doping levels). However, formulation of device model involves trade-off between accuracy and computational speed and for most practical operation such as for SPICE-based circuit simulator, empirical modeling approach is often preferred. Thus, this chapter also covers empirical modeling approaches to predict device operation by implementing mathematically fitted equations. In addition, it includes numerical device modeling approaches, which involve numerical device simulation using different types of commercial computer-based tools. Numerical models are used as virtual environment for device optimization under different conditions and the results can be used to validate the simulation models for other operating conditions

Systematic Comparison of HF CMOS Transconductors

Transconductors are commonly used as active elements in high-frequency (HF) filters, amplifiers, mixers, and oscillators. This paper reviews transconductor design by focusing on the V-I kernel that determines the key transconductor properties. Based on bandwidth considerations, simple V-I kernels with few or no internal nodes are preferred. In a systematic way, virtually all simple kernels published in literature are generated. This is done in two steps: 1) basic 3-terminal transconductors are covered and 2) then five different techniques to combine two of them in a composite V-I kernel. In order to compare transconductors in a fair way, a normalized signal-to-noise ratio (NSNR) is defined. The basic V-I kernels and the five classes of composite V-I kernels are then compared, leading to insight in the key mechanisms that affect NSNR. Symbolic equations are derived to estimate NSNR, while simulations with more advanced MOSFET models verify the results. The results show a strong tradeoff between NSNR and transconductance tuning range. Resistively generated MOSFETs render the best NSNR results and are robust for future technology developments

MODELING AND SPICE IMPLEMENTATION OF SILICON-ON-INSULATOR (SOI) FOUR GATE (G4FET) TRANSISTOR

As the device dimensions have reduced from micrometer to nanometer range, new bulk silicon devices are now facing many undesirable effects of scaling leading device engineers to look for new process technologies. Silicon-on-insulator (SOI) has emerged as a very promising candidate for resolving the major problems plaguing the bulk silicon technology. G4FET [G4FET] is a SOI transistor with four independent gates. Although G4FET has already shown great potential in different applications, the widespread adoption of a technology in circuit design is heavily dependent upon good SPICE (Simulation Program with Integrated Circuit Emphasis) models. CAD (Computer Aided Design) tools are now ubiquitous in circuit design and a fast, robust and accurate SPICE model is absolutely necessary to transform G4FET into a mainstream technology. The research goal is to develop suitable SPICE models for G4FET to aid circuit designers in designing innovative analog and digital circuits using this new transistor. The first phase of this work is numerical modeling of the G4FET where four different numerical techniques are implemented, each with its merits and demerits. The first two methods are based on multivariate Lagrange interpolation and multidimensional Bernstein polynomial. The third numerical technique is based on multivariate regression polynomial to aid modeling with dense gridded data. Another suitable alternative namely multidimensional linear and cubic spline interpolation is explored as the fourth numerical modeling approach to solve some of the problems resulting from single polynomial approximation. The next phase of modeling involves developing a macromodel combining already existing SPICE models of MOSFET (metal–oxide–semiconductor field-effect transistor) and JFET (junction-gate field-effect transistor). This model is easy to implement in circuit simulators and provides good results compared to already demonstrated experimental works with innovative G4FET circuits. The final phase of this work involves the development of a physics-based compact model of G4FET with some empirical fitting parameters. A model for depletion-all-around operation is implemented in circuit simulator based on previous work. Another simplified model, combining MOS and JFET action, is implemented in circuit simulator to model the accumulation mode operation of G4FET

A surface-potential-based compact model for partially-depleted silicon-on-insulator MOSFETs

With the continuous scaling of CMOS technologies, Silicon-on-Insulator (SOI) technologies have become more competitive compared to bulk, due to their lower parasitic capacitances and leakage currents. The shift towards high frequency, low power circuitry, coupled with the increased maturity of SOI process technologies, have made SOI a genuinely costeffective solution for leading edge applications. The original STAG2 model, developed at the University of Southampton, UK, was among the first compact circuit simulation models to specifically model the behaviour of Partially-Depleted (PD) SOI devices. STAG2 was a robust, surface-potential based compact model, employing closed-form equations to minimise simulation times for large circuits. It was able to simulate circuits in DC, small signal, and transient modes, and particular care was taken to ensure that convergence problems were kept to a minimum. In this thesis, the ongoing development of the STAG model, culminating in the release of a new version, STAG3, is described. STAG3 is intended to make the STAG model applicable to process technologies down to 100nm. To this end, a number of major model improvements were undertaken, including: a new core surface potential model, new vertical and lateral field mobility models, quantum mechanical models, the ability to model non-uniform vertical doping profiles, and other miscellaneous effects relevant to deep submicron devices such as polysilicon depletion, velocity overshoot, and the reverse short channel effect.As with the previous versions of STAG, emphasis has been placed on ensuring that model equations are numerically robust, as well as closed-form wherever possible, in order to minimise convergence problems and circuit simulation times. The STAG3 model has been evaluated with devices manufactured in PD-SOI technologies down to 0.25?m, and was found to give good matching to experimental data across a range of device sizes and biases, whilst requiring only a single set of model parameters

Improved parametric analysis of cylindrical surrounding double-gate (CSDG) MOSFET.

Masters Degree. University of KwaZulu-Natal, Durban.Transistors are major components in designing and fabricating high-speed switching devices and micro-electronics. The Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is popular and highly efficient for designing switches. It has wide applications in microelectronics, nanotechnology and Very Large-Scale Integration (VLSI) design where millions of MOSFETs are fabricated and embedded into a single chip. In these applications, heat becomes a major concern and requires to be addressed. The Cylindrical Surrounding Double-Gate (CSDG) MOSFET was introduced to overcome this challenge. The device has two scaled channel paths in a cylindrical two-gate structure, which have excellent control on the electrostatic activities that take place along the channel. This help to reduce corner effect and short channel effect and in turn produce higher drain current. This research work explores these advantages to propose a novel structure for an improved CSDG MOSFET. Firstly, the physical dimensions and structural layout of the improved CDSG MOSFET are highlighted and explained. After that, a parametric analysis of the CDSG MOSFET design has been done. This includes and supported with mathematical analysis and derivation of its operational parameters, namely surface potential, drain current, threshold voltage, transconductance, carrier mobility and capacitive characteristics etc. Thirdly, the thermal effects of this proposed device is analysed at different temperature. Also, the performance of the CDSG MOSFET is analyzed and compared to other existing MOSFET structures. The results from this analysis show that the improved CDSG MOSFET outperforms other existing MOSFETs. In fact, its power consumption is shown to be lower than those of other compared MOSFETs. A practical application of this device as an amplifier also yields plausible performance in terms of amplification gain and efficiency over a wide range of temperatures

Compact Models for Integrated Circuit Design

This modern treatise on compact models for circuit computer-aided design (CAD) presents industry standard models for bipolar-junction transistors (BJTs), metal-oxide-semiconductor (MOS) field-effect-transistors (FETs), FinFETs, and tunnel field-effect transistors (TFETs), along with statistical MOS models. Featuring exercise problems at the end of each chapter and extensive references at the end of the book, the text supplies fundamental and practical knowledge necessary for efficient integrated circuit (IC) design using nanoscale devices. It ensures even those unfamiliar with semiconductor physics gain a solid grasp of compact modeling concepts

Devenlopment of Compact Small Signal Quasi Static Models for Multiple Gate Mosfets

En esta tesis hemos desarrollado los modelos compactos explícitos de carga y de capacitancia adaptados para los dispositivos dopados y no dopados de canal largo (DG MOSFETs dopados, DG MOSFETs no dopados, UTB MOSFETs no dopados y SGT no dopados) de un modelo unificado del control de carga derivado de la ecuación de Poisson. El esquema de modelado es similar en todos estos dispositivos y se adapta a cada geometría. Los modelos de la C.C. y de la carga son completamente compatibles. Las expresiones de la capacitancia se derivan del modelo de la carga. La corriente, la carga total y las capacitancias se escriben en términos de las densidades móviles de la carga en los extremos de fuente y drenador del canal. Las expresiones explícitas e infinitamente continuas se utilizan para las densidades móviles de la carga en la fuente y drenador. Las capacitancias modeladas demuestran el acuerdo excelente con las simulaciones numéricas 2D y 3D (SGT), en todos los regímenes de funcionamiento. Por lo tanto, el modelo es muy prometedor para ser utilizado en simuladores del circuito. Desafortunadamente, no mucho trabajo se ha dedicado a este dominio de modelado. Las cargas analíticas y las capacitancias, asociadas a cada terminal se prefieren en la simulación de circuito. Con respecto al SGT MOSFET, nuestro grupo fue el primero en desarrollar y publicar un modelo de las cargas y de las capacitancias intrínsecas, que es también analítico y explícito. La tesis es organizada como sigue: el capítulo (1) presenta el estado del arte, capítulo (2) el modelado compacto de los cuatro dispositivos: DG MOSFETs dopados, DG MOSFETs no dopados, UTB MOSFETs no dopados y SGT no dopados; en el capítulo (3) estudiamos las capacitancias de fricción en MuGFETs. Finalmente el capítulo (4) resuma el trabajo hecho y los futuros objetivos que necesitan ser estudiados. Debido a la limitación de los dispositivos optimizados disponibles para el análisis, la simulación numérica fue utilizada como la herramienta principal del análisis. Sin embargo, cuando estaban disponibles, medidas experimentales fueron utilizadas para validar nuestros resultados. Por ejemplo, en la sección 2A, en el caso de DG MOSFETs altamente dopados podríamos comparar nuestros resultados con datos experimentales de FinFETs modelados como DG MOSFETs. La ventaja principal de este trabajo es el carácter analítico y explícito del modelo de la carga y de la capacitancia que las hace fácil de implementar en simuladores de circuitos. El modelo presenta los resultados casi perfectos para diversos casos del dopaje y para diversas estructuras no clásicas del MOSFET (los DG MOSFETs, los UTB MOSFETs y los SGTs). La variedad de las estructuras del MOSFET en las cuales se ha incluido nuestro esquema de modelado y los resultados obtenidos, demuestran su validez absoluta. En el capítulo 3, investigamos la influencia de los parámetros geométricos en el funcionamiento en RF de los MuGFETs. Demostramos el impacto de parámetros geométricos importantes tales como el grosor de la fuente y del drenador o, el espaciamiento de las fins, la anchura del espaciador, etc. en el componente parásito de la capacitancia de fricción de los transistores de la múltiple-puerta (MuGFET). Los resultados destacan la ventaja de disminuir el espaciamiento entre las fins para MuGFETs y la compensación entre la reducción de las resistencias parásitas de fuente y drenador y el aumento de capacitancias de fricción cuando se introduce la tecnología del crecimiento selectivo epitaxial (SEG). La meta de nuestro estudio y trabajo es el uso de nuestros modelos en simuladores de circuitos. El grupo de profesor Aranda, de la Universidad de Granada ha puesto el modelo actual de SGT en ejecución en el simulador Agilent ADS y buenos resultados fueron obtenidos.In this thesis we have developed explicit compact charge and capacitance models adapted for doped and undoped long-channel devices (doped Double-Gate (DG) MOSFETs, undoped DG MOSFETs, undoped Ultra-Thin-Body (UTB) MOSFETs and undoped Surrounding Gate Transistor (SGT)) from a unified charge control model derived from Poisson's equation. The modelling scheme is similar in all these devices and is adapted to each geometry. The dc and charge models are fully compatible. The capacitance expressions are derived from the charge model. The current, total charges and capacitances are written in terms of the mobile charge sheet densities at the source and drain ends of the channel. Explicit and infinitely continuous expressions are used for the mobile charge sheet densities at source and drain. As a result, all small signal parameters will have an infinite order of continuity. The modeled capacitances show excellent agreement with the 2D and 3D (SGT) numerical simulations, in all operating regimes. Therefore, the model is very promising for being used in circuit simulators. Unfortunately, not so much work has been dedicated to this modelling domain. Analytical charges and capacitances, associated with each terminal are preferred in circuit simulation. Regarding the surrounding-gate MOSFET, our group was the first to develop and publish a model of the charges and intrinsic capacitances, which is also analytic and explicit. The thesis is organized as follows: Chapter (1) presents the state of the art, Chapter (2) the compact modeling of the four devices: doped DG MOSFETs, undoped DG MOSFETs, undoped UTB MOSFETs and undoped SGT; in Chapter (3) we study the fringing capacitances in MuGFETs. Finally Chapter (4) summarizes the work done and the future points that need to be studied. Due to the limitation of available optimized devices for analysis, numerical simulation was used as the main analysis tool. However, when available, measurements were used to validate our results. The experimental part was realised at the Microelectronics Laboratory, Université Catholique de Louvain, Louvain-la Neuve, Belgium. For example, in section 2A, in the case of highly-doped DG MOSFETs we could compare our results with experimental data from FinFETs modeled as DG MOSFETs. The main advantage of this work is the analytical and explicit character of the charge and capacitance model that makes it easy to implement in circuit simulators. The model presents almost perfect results for different cases of doping (doped/undoped devices) and for different non classical MOSFET structures (DG MOSFET, UTB MOSFETs and SGT). The variety of the MOSFET structures in which our modeling scheme has been included and the obtained results, demonstrate its absolute validity. In chapter 3, we investigate the influence of geometrical parameters on the RF performance in MuGFETs. We show the impact of important geometrical parameters such as source and drain thickness, fin spacing, spacer width, etc. on the parasitic fringing capacitance component of multiple-gate field-effect transistors (MuGFET). Results highlight the advantage of diminishing the spacing between fins for MuGFETs and the trade-off between the reduction of parasitic source and drain resistances and the increase of fringing capacitances when Selective Epitaxial Growth (SEG) technology is introduced. The goal of our study and work is the usage of our models in circuit simulators. This part, of implementing and testing our models of these multi gate MOSFET devices in circuit simulators has already begun. The group of Professor Aranda, from the University of Granada has implemented the SGT current model in the circuit simulator Agilent ADS and good results were obtained

MOSFET zero-temperature-coefficient (ZTC) effect modeling anda analysis for low thermal sensitivity analog applications

Continuing scaling of Complementary Metal-Oxide-Semiconductor (CMOS) technologies brings more integration and consequently temperature variation has become more aggressive into a single die. Besides, depending on the application, room ambient temperature may also vary. Therefore, procedures to decrease thermal dependencies of eletronic circuit performances become an important issue to include in both digital and analog Integrated Circuits (IC) design flow. The main purpose of this thesis is to present a design methodology for a typical CMOS Analog design flow to make circuits as insensitivity as possible to temperature variation. MOSFET Zero Temperature Coefficient (ZTC) and Transconductance Zero Temperature Coefficient (GZTC) bias points are modeled to support it. These are used as reference to deliver a set of equations that explains to analog designers how temperature will change transistor operation and hence the analog circuit behavior. The special bias conditions are analyzed using a MOSFET model that is continuous from weak to strong inversion, and both are proven to occur always from moderate to strong inversion operation in any CMOS fabrication process. Some circuits are designed using proposed methodology: two new ZTC-based current references, two new ZTC-based voltage references and four classical Gm-C circuits biased at GZTC bias point (or defined here as GZTC-C filters). The first current reference is a Self-biased CMOS Current Reference (ZSBCR), which generates a current reference of 5 A. It is designed in an 180 nm process, operating with a supply voltage from 1.4V to 1.8 V and occupying around 0:010mm2 of silicon area. From circuit simulations the reference shows an effective temperature coefficient (TCeff ) of 15 ppm/oC from 45 to +85oC, and a fabrication process sensitivity of = = 4:5%, including average process and local mismatch. Simulated power supply sensitivity is estimated around 1%/V. The second proposed current reference is a Resistorless Self-Biased ZTC Switched Capacitor Current Reference (ZSCCR). It is also designed in an 180 nm process, resulting a reference current of 5.88 A under a supply voltage of 1.8 V, and occupying a silicon area around 0:010mm2. Results from circuit simulation show an TCeff of 60 ppm/oC from -45 to +85 oC and a power consumption of 63 W. The first proposed voltage reference is an EMI Resisting MOSFET-Only Voltage Reference (EMIVR), which generates a voltage reference of 395 mV. The circuit is designed in a 130 nm process, occupying around 0.0075 mm2 of silicon area while consuming just 10.3 W. Post-layout simulations present a TCeff of 146 ppm/oC, for a temperature range from 55 to +125oC. An EMI source of 4 dBm (1 Vpp amplitude) injected into the power supply of circuit, according to Direct Power Injection (DPI) specification results in a maximum DC Shift and Peak-to-Peak ripple of -1.7 % and 35.8m Vpp, respectively. The second proposed voltage reference is a 0.5V Schottky-based Voltage Reference (SBVR). It provides three voltage reference outputs, each one utilizing different threshold voltage MOSFETs (standard-VT , low-VT , and zero-VT ), all available in adopted 130 nm CMOS process. This design results in three different and very low reference voltages: 312, 237, and 51 mV, presenting a TCeff of 214, 372, and 953 ppm/oC in a temperature range from -55 to 125oC, respectively. It occupies around 0.014 mm2 of silicon area for a total power consumption of 5.9 W. Lastly, a few example Gm-C circuits are designed using GZTC technique: a single-ended resistor emulator, an impedance inverter, a first order and a second order filter. These circuits are simulated in a 130 nm CMOS commercial process, resulting improved thermal stability in the main performance parameters, in the range from 27 to 53 ppm/°C.A contínua miniaturização das tecnologias CMOS oferece maior capacidade de integração e, consequentemente, as variações de temperatura dentro de uma pastilha de silício têm se apresentado cada vez mais agressivas. Ademais, dependendo da aplicação, a temperatura ambiente a qual o CHIP está inserido pode variar. Dessa maneira, procedimentos para diminuir o impacto dessas variações no desempenho do circuito são imprescindíveis. Tais métodos devem ser incluídos em ambos fluxos de projeto CMOS, analógico e digital, de maneira que o desempenho do sistema se mantenha estável quando a temperatura oscilar. A ideia principal desta dissertação é propor uma metodologia de projeto CMOS analógico que possibilite circuitos com baixa dependência térmica. Como base fundamental desta metodologia, o efeito de coeficiente térmico nulo no ponto de polarização da corrente de dreno (ZTC) e da transcondutância (GZTC) do MOSFET são analisados e modelados. Tal modelamento é responsável por entregar ao projetista analógico um conjunto de equações que esclarecem como a temperatura influencia o comportamento do transistor e, portanto, o comportamento do circuito. Essas condições especiais de polarização são analisadas usando um modelo de MOSFET que é contínuo da inversão fraca para forte. Além disso, é mostrado que as duas condições ocorrem em inversão moderada para forte em qualquer processo CMOS. Algumas aplicações são projetadas usando a metodologia proposta: duas referências de corrente baseadas em ZTC, duas referências de tensão baseadas em ZTC, e quatro circuitos gm-C polarizados em GZTC. A primeira referência de corrente é uma Corrente de Referência CMOS Auto-Polarizada (ZSBCR), que gera uma referência de 5uA. Projetada em CMOS 180 nm, a referência opera com uma tensão de alimentação de 1.4 à 1.8 V, ocupando uma área em torno de 0:010mm2. Segundo as simulações, o circuito apresenta um coeficiente de temperatura efetivo (TCeff ) de 15 ppm/oC para -45 à +85 oC e uma sensibilidade à variação de processo de = = 4:5% incluindo efeitos de variabilidade dos tipos processo e descasamento local. A sensibilidade de linha encontrada nas simulações é de 1%=V . A segunda referência de corrente proposta é uma Corrente de Referência Sem Resistor Auto-Polarizada com Capacitor Chaveado (ZSCCR). O circuito é projetado também em 180 nm, resultando em uma corrente de referência de 5.88 A, para uma tensão de alimentação de 1.8 V, e ocupando uma área de 0:010mm2. Resultados de simulações mostram um TCeff de 60 ppm/oC para um intervalo de temperatura de -45 à +85 oC e um consumo de potência de 63 W. A primeira referência de tensão proposta é uma Referência de Tensão resistente à pertubações eletromagnéticas contendo apenas MOSFETs (EMIVR), a qual gera um valor de referência de 395 mV. O circuito é projetado no processo CMOS 130 nm, ocupando em torno de 0.0075 mm2 de área de silício, e consumindo apenas 10.3 W. Simulações pós-leiaute apresentam um TCeff de 146 ppm/oC, para um intervalo de temperatura de 55 à +125oC. Uma fonte EMI de 4 dBm (1 Vpp de amplitude) aplicada na alimentação do circuito, de acordo com o padrão Direct Power Injection (DPI), resulta em um máximo de desvio DC e ondulação Pico-à-Pico de -1.7 % e 35.8m Vpp, respectivamente. A segunda referência de tensão é uma Tensão de Referência baseada em diodo Schottky com 0.5V de alimentação (SBVR). Ela gera três saídas, cada uma utilizando MOSFETs com diferentes tensões de limiar (standard-VT , low-VT , e zero-VT ). Todos disponíveis no processo adotado CMOS 130 nm. Este projeto resulta em três diferentes voltages de referências: 312, 237, e 51 mV, apresentando um TCeff de 214, 372, e 953 ppm/oC no intervalo de temperatura de -55 à 125oC, respectivamente. O circuito ocupa em torno de 0.014 mm2, consumindo um total de 5.9 W. Por último, circuitos gm-C são projetados usando o conceito GZTC: um emulador de resistor, um inversor de impedância, um filtro de primeira ordem e um filtro de segunda ordem. Os circuitos também são simulados no processo CMOS 130 nm, resultando em uma melhora na estabilidade térmica dos seus principais parâmetros, indo de 27 à 53 ppm/°C