Requirements for a Research-oriented IC Design System

Computer-aided design techniques for integrated circuits grown in an incremental way, responding to various perceived needs, so that today there are a number of useful programs for logic generation, simulation at various levels, test preparation, artwork generation and analysis (including design rule checking), and interactive graphical editing. While the design of many circuits has benefitted from these programs, when industry wants to produce a high-volume part, the design and layout are done manually, followed by digitizing and perhaps some graphic editing before it is converted to pattern generation format, leading to the often heard statement that computer-aided design of integrated circuits doesn't work. If progress is to be made, it seems clear that the entire design process has to be thought through in basic terms, and much more attention must be paid to the way in which computational techniques can complement the designer's abilities. Currently, it is appropriate to try to characterize the design process in abstract terms, so that implementation and technological biases don't cloud the view of a desired system. In this paper, we briefly describe the conversion of algorithms to masks at a very general level, and then describe several projects at MIT which aim to provide contributions to an integrated design system. It is emphasized that no complete system design exists now at MIT, and that we believe that general design considerations must constantly be tested by building (and rebuilding) the various subcomponents, the structure of which is guided by our view of the overall design process

Similarity measures for mid-surface quality evaluation

Mid-surface models are widely used in engineering analysis to simplify the analysis of thin-walled parts, but it can be difficult to ensure that the mid-surface model is representative of the solid part from which it was generated. This paper proposes two similarity measures that can be used to evaluate the quality of a mid-surface model by comparing it to a solid model of the same part. Two similarity measures are proposed; firstly a geometric similarity evaluation technique based on the Hausdorff distance and secondly a topological similarity evaluation method which uses geometry graph attributes as the basis for comparison. Both measures are able to provide local and global similarity evaluation for the models. The proposed methods have been implemented in a software demonstrator and tested on a selection of representative models. They have been found to be effective for identifying geometric and topological errors in mid-surface models and are applicable to a wide range of practical thin-walled designs

Digitally interpreting traditional folk crafts

The cultural heritage preservation requires that objects persist throughout time to continue to communicate an intended meaning. The necessity of computer-based preservation and interpretation of traditional folk crafts is validated by the decreasing number of masters, fading technologies, and crafts losing economic ground. We present a long-term applied research project on the development of a mathematical basis, software tools, and technology for application of desktop or personal fabrication using compact, cheap, and environmentally friendly fabrication devices, including '3D printers', in traditional crafts. We illustrate the properties of this new modeling and fabrication system using several case studies involving the digital capture of traditional objects and craft patterns, which we also reuse in modern designs. The test application areas for the development are traditional crafts from different cultural backgrounds, namely Japanese lacquer ware and Norwegian carvings. Our project includes modeling existing artifacts, Web presentations of the models, automation of the models fabrication, and the experimental manufacturing of new designs and forms

Testing times: on model-driven test generation for non-deterministic real-time systems

Summary form only given. Although testing has always been the most important technique for the validation of software systems it has only become a topic of serious academic research in the past decade or so. In this period research on the use of formal methods for model-driven test generation and execution of functional test cases has led to a number of promising methods and tools for systematic black-box testing of systems, examples are based on A. Belinfante et al. (1999), J. Tretmans and E. Brinksma (2003), J.-C. Fernandez et al. (1996) and J.-C. Fernandez et al. (1997). Most of these approaches are limited to the qualitative behaviour of systems, and exclude quantitative aspects such as real-time properties. The explosive growth of embedded software, however, has also caused a growing need to extend existing testing theories to the testing of real-time reactive systems. In our presentation we present an extension of Tretmans' ioco theory for test generation as stated in J. Tretmans (1996) for input/output transition systems that includes real-time behaviour

Incremental bounded model checking for embedded software

Program analysis is on the brink of mainstream usage in embedded systems development. Formal verification of behavioural requirements, finding runtime errors and test case generation are some of the most common applications of automated verification tools based on bounded model checking (BMC). Existing industrial tools for embedded software use an off-the-shelf bounded model checker and apply it iteratively to verify the program with an increasing number of unwindings. This approach unnecessarily wastes time repeating work that has already been done and fails to exploit the power of incremental SAT solving. This article reports on the extension of the software model checker CBMC to support incremental BMC and its successful integration with the industrial embedded software verification tool BTC EMBEDDED TESTER. We present an extensive evaluation over large industrial embedded programs, mainly from the automotive industry. We show that incremental BMC cuts runtimes by one order of magnitude in comparison to the standard non-incremental approach, enabling the application of formal verification to large and complex embedded software. We furthermore report promising results on analysing programs with arbitrary loop structure using incremental BMC, demonstrating its applicability and potential to verify general software beyond the embedded domain