1,944 research outputs found
High volume colour image processing with massively parallel embedded processors
Currently Oc´e uses FPGA technology for implementing colour image processing for their high volume colour printers. Although FPGA technology provides enough performance it, however, has a rather tedious development process. This paper describes the research conducted on an alternative implementation technology: software defined massively parallel processing. It is shown that this technology not only leads to a reduction in development time but also adds flexibility to the design
Document Classification Systems in Heterogeneous Computing Environments
Datacenter workloads demand high throughput, low cost and power efficient solutions. In most data centers the operating costs dominates the infrastructure cost. The ever growing amounts of data and the critical need for higher throughput, more energy efficient document classification solutions motivated us to investigate alternatives to the traditional homogeneous CPU based implementations of document classification systems. Several heterogeneous systems were investigated in the past where CPUs were combined with GPUs and FPGAs as system accelerators. The increasing complexity of FPGAs made them an interesting device in the heterogeneous computing environments and on the other hand difficult to program using Hardware Description languages. We explore the trade-offs when using high level synthesis and low level synthesis when programming FPGAs. Using low level synthesis results in less hardware resource usage on FPGAs and also offers the higher throughput compared to using HLS tool. While using HLS tool different heterogeneous computing devices such as multicore CPU and GPU targeted. Through our implementation experience and empirical results for data centric applications, we conclude that we can achieve power efficient results for these set of applications by either using low level synthesis or high level synthesis for programming FPGAs
EChO Payload electronics architecture and SW design
EChO is a three-modules (VNIR, SWIR, MWIR), highly integrated spectrometer,
covering the wavelength range from 0.55 m, to 11.0 m. The baseline
design includes the goal wavelength extension to 0.4 m while an optional
LWIR module extends the range to the goal wavelength of 16.0 m.
An Instrument Control Unit (ICU) is foreseen as the main electronic subsystem
interfacing the spacecraft and collecting data from all the payload
spectrometers modules. ICU is in charge of two main tasks: the overall payload
control (Instrument Control Function) and the housekeepings and scientific data
digital processing (Data Processing Function), including the lossless
compression prior to store the science data to the Solid State Mass Memory of
the Spacecraft. These two main tasks are accomplished thanks to the Payload On
Board Software (P-OBSW) running on the ICU CPUs.Comment: Experimental Astronomy - EChO Special Issue 201
Fast self-reconfigurable embedded system on Spartan-3
Many image-processing algorithms require several stages to be processed that cannot
be resolved by embedded microprocessors in a reasonable time, due to their high-computational
cost. A set of dedicated coprocessors can accelerate the resolution of these algorithms, alt
hough
the main drawback is the area needed for their implementation. The main advantage of a
reconfigurable system is that several coprocessors designed to perform different operations can
be mapped on the same area in a time-multiplexed
way. This work presents the architecture of
an embedded system composed of a microprocessor and a run-time reconfigurable coprocessor,
mapped on Spartan-3, the low-cost family of Xilinx FPGAs. Designing reconfigurable systems
on Spartan-3 requires much design effort, since unlike higher cost families of Xilinx FPGAs,
this device does not officially support partial reconfiguration. In order to overcome this
drawback, the paper also describes the main steps used in the design flow to obtain a successful
design. The main goal of the presented architecture is to reduce the coprocessor reconfiguration
time, as well as accelerate image-processing algorithms. The experimental results demonstrate
significant improvement in both objectives. The reconfiguration rate nearly achieves 320 Mb/s
which is far superior to th
e previous related works.Peer ReviewedPostprint (published version
A committee machine gas identification system based on dynamically reconfigurable FPGA
This paper proposes a gas identification system based on the committee machine (CM) classifier, which combines various gas identification algorithms, to obtain a unified decision with improved accuracy. The CM combines five different classifiers: K nearest neighbors (KNNs), multilayer perceptron (MLP), radial basis function (RBF), Gaussian mixture model (GMM), and probabilistic principal component analysis (PPCA). Experiments on real sensors' data proved the effectiveness of our system with an improved accuracy over individual classifiers. Due to the computationally intensive nature of CM, its implementation requires significant hardware resources. In order to overcome this problem, we propose a novel time multiplexing hardware implementation using a dynamically reconfigurable field programmable gate array (FPGA) platform. The processing is divided into three stages: sampling and preprocessing, pattern recognition, and decision stage. Dynamically reconfigurable FPGA technique is used to implement the system in a sequential manner, thus using limited hardware resources of the FPGA chip. The system is successfully tested for combustible gas identification application using our in-house tin-oxide gas sensors
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