Low power memory allocation and mapping for area-constrained systems-on-chips

Large fractions of today’s embedded systems’ power consumption can be attributed to the memory subsystem. In order to reduce this fraction, we propose a mathematical model to optimize on-chip memory configurations for minimal power. We exploit the power reduction effect of splitting memory into subunits with frequently accessed addresses mapped to small memories. The definition of an integer linear programming model enables us to solve the twofold problem of allocating an optimal set of memory instances with varying size on the one hand and finding an optimal mapping of application segments to allocated memories on the other hand. Experimental results yield power reductions of up to 82 % for instruction memory and 73 % for data memory. Area usage, at the same time, deteriorates by only 2.1 %, respectively, 1.2 % on average and even improves in some cases. Flexibility and performance of our model make it a valuable tool for low power system-on-chip design, either for efficient design space exploration or as part of a HW/SW codesign synthesis flow

Schedulability-driven scratchpad memory swapping for resource-constrained real-time embedded systems

In resource-constrained real-time embedded systems, scratchpad memory (SPM) is utilized in place of cache to increase performance and enforce consistent behavior of both hard and soft real-time tasks via software-controlled SPM management techniques (SPMMTs). Real-time systems depend on time critical (hard) tasks to complete execution before their deadline times. Many real-time systems also depend on the execution of soft tasks that do not have to complete by hard deadlines. This thesis evaluates a new SPMMT that increases both worst-case task slack time (TST) and soft task processing capabilities, by combining two existing SPMMTs. The schedulability-driven ACETRB / WCETRB swapping (SDAWS) SPMMT of this thesis uses task schedulability characteristics to control the selection of either the average-case execution time reduction based (ACETRB) SPMMT or the worst-case execution time reduction based (WCETRB) SPMMT. While the literature contains examples of combined management techniques, until now there have been none that combine both WCETRB and ACETRB SPMMTs. The advantage of combining them is to achieve WCET reduction comparable to what can be achieved with the WCETRB SPMMT, while achieving significantly reduced ACET relative to the WCETRB SPMMT. Using a stripped-down RTOS and an SPMMT simulator implemented for this work, evaluated resource-constrained scenarios show a reduction in task slack time from the SDAWS SPMMT relative to the WCETRB SPMMT between 20% and 45%. However, the evaluated scenarios also conservatively show that SDAWS can reduce ACET relative to the WCETRB SPMMT by up to 60%

An Efficient Profile-Based Algorithm for Scratchpad Memory Partitioning

Focusing on embedded applications, scratchpad memories (SPMs) look like a best-compromise solution when taking into account performance, energy consumption and die area. The main challenge in SPM design is to optimally map memory locations to scratchpad locations. This paper describes an algorithm to solve such a mapping problem by means of Dynamic Programming applied to a synthesizable hardware architecture. The algorithm works by mapping segments of external memory to physically partitioned banks of an on-chip SPM; this architecture provides significant energy savings. The algorithm does not require any user-set bound on the number of partitions and takes into account partitioning overhead. Improving on previous solutions, execution time is polynomial in the number of memory locations, even in the most general solving policy. This has the major practical advantage of allowing an arbitrary number of scratchpad segments, something that was impossible with previous methods, whose running time is exponential in this number. Strategies to optimize memory requirements and speed of the algorithm are exploited. Additionally, we integrate this algorithm in a complete and automated design, simulation and synthesis flow

Contribution au domaine de la conception des Systèmes Embarqués et Pervasifs Faible Consommation

La première partie est consacré à l’Estimation de la Consommation des Architectures Logicel. Ce travail est en continuité de mes travaux de thèse et ont démarré avec le projet SPICES piloté par le Dr Eric Senn. Ce projet avait pour but, pour notre partie, de modéliser et d’estimer la consommation des services d’un système d’exploitation à haut niveau. Ces travaux ont fait l’objet de la thèse de Saadia Dhouib (2006-2009) co dirigée par Eric Senn et Jean Philippe Diguet.La seconde aborde le problème du placement des données en mémoire pour les architectures logiciel. L’idée de ces travaux était de permettre un placement optimum des structures de données d’une application dans une hiérarchie mémoire fixée. Ce travail a été le début de la collaboration avec Marc Sevaux et André Rossi sur ces aspects et ont été poursuivis dans la thèse réalisée par Maria Soto (2008-2011).La troisième présente les travaux autour de l’estimation et l’optimisation de la consommation des interconnexions dans les systèmes sur puce (SoC). Dans un système sur puce la consommation d’énergie générée par les interconnexions peut devenir non négligeable ; il devient donc indispensable de pouvoir optimiser cette consommation. Afin de pouvoir juger des optimisations proposées, un modèle d’estimation est nécessaire car le temps de conception et de simulation (au niveau électrique) est prohibitif. Ces travaux ont fait l’objet de la thèse d’Antoine Courtay (2005-2008) co dirigée par Olivier Sentieys et Nathalie Julien.Enfin la dernière aborde mes derniers travaux de recherche sur la conception de systèmes pervasifs pour le domaine maritime. Ces travaux aborde plusieurs sous thèmes comme: -la mesure de la performance pour la course au large ; travaux de thèse de Ronan Douguet (2010-2014)-l’utilisation de la réalité augmentée pour l’aide à la navigation ; travaux de thèse de Jean Christophe Morgère (2011-2015)-l’optimisation temps réel d’énergies renouvelables pour voilier du futur ; travaux de thèse de Mathilde Tréhin (2013- ?)-les algorithmes et plateforme faible consommation pour la conception d’un pilote automatique haute performance pour le nautisme ; travaux de thèse d’Hugo Kerhascoet (2014-2017

Automated Compilation Framework for Scratchpad-based Real-Time Systems

ScratchPad Memory (SPM) is highly adopted in real-time systems as it exhibits a predictable behaviour. SPM is software-managed by explicitly inserting instructions to move code and data transfers between the SPM and the main memory. However, it is a tedious job to decide how to manage the SPM and to manually modify the code to insert memory transfers. Hence, an automated compilation tool is essential to efficiently utilize the SPM. Another key problem with SPM is the latency suffered by the system due to memory transfers. Hiding this latency is important for high-performance systems. In this thesis, we address the problems of managing SPM and reducing the impact of memory latency. To realize the automation of our work, we develop a compilation framework based on the LLVM compiler to analyze and transform the program code. We exploit our framework to improve the performance of the execution of single and multi-tasks in real-time systems. For the single task execution, Worst-Case Execution Time (WCET) is of great importance to assure correct and safe behaviour of the system. So, we propose a WCET-driven allocation technique for data SPM that employs software prefetching to efficiently manage the SPM and to overlap the memory transfer and the task execution in a predictable way. On the other hand, multi-tasking requires the system to be schedulable such that all the tasks can meet their timing requirements. However, executing multiple tasks on a multi-processor platform suffers from the contention of the accesses to the shared main memory. To avoid the contention, several scheduling techniques adopted the 3-phase execution model which executes the task as a sequence of memory and computation phases. This provides the means to avoid the contention as well as to hide the memory latency by using a Direct Memory Access (DMA) engine. Executing memory transfers using the DMA allows overlapping the memory transfers with the computations on the processor. Using the 3-phase model in systems with limited sizes of local SPM may necessitate a segmentation of the task. Automating the segmentation process is necessary especially for systems with large task sets. Hence, we propose a set of efficient segmentation algorithms that follow the 3-phase execution model. The application of these algorithms shows a significant improvement in the system schedulability. For our segmentation algorithms to be more applicable, we extend the 3-phase model to allow programs with multiple paths represented as conditional Directed Acyclic Graphs (DAGs), unlike the previous works that targeted sequential programs. We also introduce a multi-steaming model to exploit the benefits of prefetching by overlapping the memory and computation phases of the same task, which was not allowed in the previous approaches. By combining the automated compilation with the proposed algorithms, we are able to achieve our goal to efficiently manage data SPM in real-time systems