MOSFET zero-temperature-coefficient (ZTC) effect modeling anda analysis for low thermal sensitivity analog applications

Continuing scaling of Complementary Metal-Oxide-Semiconductor (CMOS) technologies brings more integration and consequently temperature variation has become more aggressive into a single die. Besides, depending on the application, room ambient temperature may also vary. Therefore, procedures to decrease thermal dependencies of eletronic circuit performances become an important issue to include in both digital and analog Integrated Circuits (IC) design flow. The main purpose of this thesis is to present a design methodology for a typical CMOS Analog design flow to make circuits as insensitivity as possible to temperature variation. MOSFET Zero Temperature Coefficient (ZTC) and Transconductance Zero Temperature Coefficient (GZTC) bias points are modeled to support it. These are used as reference to deliver a set of equations that explains to analog designers how temperature will change transistor operation and hence the analog circuit behavior. The special bias conditions are analyzed using a MOSFET model that is continuous from weak to strong inversion, and both are proven to occur always from moderate to strong inversion operation in any CMOS fabrication process. Some circuits are designed using proposed methodology: two new ZTC-based current references, two new ZTC-based voltage references and four classical Gm-C circuits biased at GZTC bias point (or defined here as GZTC-C filters). The first current reference is a Self-biased CMOS Current Reference (ZSBCR), which generates a current reference of 5 A. It is designed in an 180 nm process, operating with a supply voltage from 1.4V to 1.8 V and occupying around 0:010mm2 of silicon area. From circuit simulations the reference shows an effective temperature coefficient (TCeff ) of 15 ppm/oC from 45 to +85oC, and a fabrication process sensitivity of = = 4:5%, including average process and local mismatch. Simulated power supply sensitivity is estimated around 1%/V. The second proposed current reference is a Resistorless Self-Biased ZTC Switched Capacitor Current Reference (ZSCCR). It is also designed in an 180 nm process, resulting a reference current of 5.88 A under a supply voltage of 1.8 V, and occupying a silicon area around 0:010mm2. Results from circuit simulation show an TCeff of 60 ppm/oC from -45 to +85 oC and a power consumption of 63 W. The first proposed voltage reference is an EMI Resisting MOSFET-Only Voltage Reference (EMIVR), which generates a voltage reference of 395 mV. The circuit is designed in a 130 nm process, occupying around 0.0075 mm2 of silicon area while consuming just 10.3 W. Post-layout simulations present a TCeff of 146 ppm/oC, for a temperature range from 55 to +125oC. An EMI source of 4 dBm (1 Vpp amplitude) injected into the power supply of circuit, according to Direct Power Injection (DPI) specification results in a maximum DC Shift and Peak-to-Peak ripple of -1.7 % and 35.8m Vpp, respectively. The second proposed voltage reference is a 0.5V Schottky-based Voltage Reference (SBVR). It provides three voltage reference outputs, each one utilizing different threshold voltage MOSFETs (standard-VT , low-VT , and zero-VT ), all available in adopted 130 nm CMOS process. This design results in three different and very low reference voltages: 312, 237, and 51 mV, presenting a TCeff of 214, 372, and 953 ppm/oC in a temperature range from -55 to 125oC, respectively. It occupies around 0.014 mm2 of silicon area for a total power consumption of 5.9 W. Lastly, a few example Gm-C circuits are designed using GZTC technique: a single-ended resistor emulator, an impedance inverter, a first order and a second order filter. These circuits are simulated in a 130 nm CMOS commercial process, resulting improved thermal stability in the main performance parameters, in the range from 27 to 53 ppm/°C.A contínua miniaturização das tecnologias CMOS oferece maior capacidade de integração e, consequentemente, as variações de temperatura dentro de uma pastilha de silício têm se apresentado cada vez mais agressivas. Ademais, dependendo da aplicação, a temperatura ambiente a qual o CHIP está inserido pode variar. Dessa maneira, procedimentos para diminuir o impacto dessas variações no desempenho do circuito são imprescindíveis. Tais métodos devem ser incluídos em ambos fluxos de projeto CMOS, analógico e digital, de maneira que o desempenho do sistema se mantenha estável quando a temperatura oscilar. A ideia principal desta dissertação é propor uma metodologia de projeto CMOS analógico que possibilite circuitos com baixa dependência térmica. Como base fundamental desta metodologia, o efeito de coeficiente térmico nulo no ponto de polarização da corrente de dreno (ZTC) e da transcondutância (GZTC) do MOSFET são analisados e modelados. Tal modelamento é responsável por entregar ao projetista analógico um conjunto de equações que esclarecem como a temperatura influencia o comportamento do transistor e, portanto, o comportamento do circuito. Essas condições especiais de polarização são analisadas usando um modelo de MOSFET que é contínuo da inversão fraca para forte. Além disso, é mostrado que as duas condições ocorrem em inversão moderada para forte em qualquer processo CMOS. Algumas aplicações são projetadas usando a metodologia proposta: duas referências de corrente baseadas em ZTC, duas referências de tensão baseadas em ZTC, e quatro circuitos gm-C polarizados em GZTC. A primeira referência de corrente é uma Corrente de Referência CMOS Auto-Polarizada (ZSBCR), que gera uma referência de 5uA. Projetada em CMOS 180 nm, a referência opera com uma tensão de alimentação de 1.4 à 1.8 V, ocupando uma área em torno de 0:010mm2. Segundo as simulações, o circuito apresenta um coeficiente de temperatura efetivo (TCeff ) de 15 ppm/oC para -45 à +85 oC e uma sensibilidade à variação de processo de = = 4:5% incluindo efeitos de variabilidade dos tipos processo e descasamento local. A sensibilidade de linha encontrada nas simulações é de 1%=V . A segunda referência de corrente proposta é uma Corrente de Referência Sem Resistor Auto-Polarizada com Capacitor Chaveado (ZSCCR). O circuito é projetado também em 180 nm, resultando em uma corrente de referência de 5.88 A, para uma tensão de alimentação de 1.8 V, e ocupando uma área de 0:010mm2. Resultados de simulações mostram um TCeff de 60 ppm/oC para um intervalo de temperatura de -45 à +85 oC e um consumo de potência de 63 W. A primeira referência de tensão proposta é uma Referência de Tensão resistente à pertubações eletromagnéticas contendo apenas MOSFETs (EMIVR), a qual gera um valor de referência de 395 mV. O circuito é projetado no processo CMOS 130 nm, ocupando em torno de 0.0075 mm2 de área de silício, e consumindo apenas 10.3 W. Simulações pós-leiaute apresentam um TCeff de 146 ppm/oC, para um intervalo de temperatura de 55 à +125oC. Uma fonte EMI de 4 dBm (1 Vpp de amplitude) aplicada na alimentação do circuito, de acordo com o padrão Direct Power Injection (DPI), resulta em um máximo de desvio DC e ondulação Pico-à-Pico de -1.7 % e 35.8m Vpp, respectivamente. A segunda referência de tensão é uma Tensão de Referência baseada em diodo Schottky com 0.5V de alimentação (SBVR). Ela gera três saídas, cada uma utilizando MOSFETs com diferentes tensões de limiar (standard-VT , low-VT , e zero-VT ). Todos disponíveis no processo adotado CMOS 130 nm. Este projeto resulta em três diferentes voltages de referências: 312, 237, e 51 mV, apresentando um TCeff de 214, 372, e 953 ppm/oC no intervalo de temperatura de -55 à 125oC, respectivamente. O circuito ocupa em torno de 0.014 mm2, consumindo um total de 5.9 W. Por último, circuitos gm-C são projetados usando o conceito GZTC: um emulador de resistor, um inversor de impedância, um filtro de primeira ordem e um filtro de segunda ordem. Os circuitos também são simulados no processo CMOS 130 nm, resultando em uma melhora na estabilidade térmica dos seus principais parâmetros, indo de 27 à 53 ppm/°C

Uma referência de tensão CMOS integrada utilizando transistor composto cascode e diodo Schottky

This work shows a study of temperature behavior of self-cascode composite transistors (SCCTs) and Schottky diode in order to generate both PTAT and CTAT voltages of a temperature-compensated voltage reference. The SCCTs study also shows that it is possible to obtain a compensated voltage with a proper sizing and biasing of the SCCT. The voltage reference was designed based on achieved results and it was fabricated in a 130 nm CMOS process. The circuit occupies an area of 67.98 μm x 161.7 μm and it was measured in temperature and power-supply variation. A trimming circuit also is added to the reference in order to adjust the temperature coefficient (TC). The averaged output voltage is 720 mV with a VDD of 1.1 V. The averaged TC is 56 ppm/ºC in a temperature range of -40 to 85 ºC. The circuit works in a power-supply range of 1.1 to 2.5 V and its power consumption is 750 nW.Agência 1Este trabalho apresenta o estudo da performance em temperatura de self-cascode composite transistors (SCCTs) e do diodo Schottky com o objetivo de gerar as tensões PTAT e CTAT, respectivamente, que compõem uma referência de tensão compensada na temperatura. O estudo dos SCCTs também mostrou ser possível obter uma tensão compensada apenas ajustando a dimensão e o ponto de operação dos transistores que formam o SCCT. A referência foi projetada baseada nestes resultados e fabricada em um processo CMOS 130 nm. O circuito ocupa uma área de 67,98 μm x 161,7 μm. Para validação do projeto, o circuito foi medido com a variação de temperatura e tensão de alimentação. Um circuito de ajuste também foi projetado para ajustar o coeficiente de temperatura da referência (TC). A tensão de saída média obtida foi de 720 mV em um VDD de 1,1 V. O TC médio obtido foi 56 ppm/ºC em uma faixa de temperatura de -40 a 85 ºC. O circuito opera em uma faixa e tensão de alimentação de 1,1 a 2,5 V. O consumo do circuito é de 750 nW

CMOS analog-digital circuit components for low power applications

Dissertação de mestrado em Micro and NanoelectronicsThis dissertation presents a study in the area of mixed analog/digital CMOS power extraction circuits for energy harvester. The main contribution of this work is the realization of low power consumption and high efficient circuit components employable in a management circuit for piezoelectricbased energy harvester. This thesis focuses on the development of current references and operational amplifiers addressing low power demands. A brief literature review is conducted on the components necessary for the power extraction circuit, including introduction to CMOS technology design and research of known low power circuits. It is presented with multiple implementations for voltage and current references, as well for operational amplifier designs. A self-biased current reference, capable of driving the remaining harvesting circuit, is designed and verified. A novel operational amplifier is proposed by the use of a minimum current selector circuit topology. It is a three-stage amplifier with an AB class output stage, comprised by a translinear circuit. The circuit is designed, taking into consideration noise reduction. The circuit components are designed based on the 0.35mm CMOS technology. A physical layout is developed for fabrication purposes. This technology was chosen with consideration of robustness, costliness and performance. The current reference is capable of outputting a stable 12nA current, which may remain stable in a broad range of power supply voltages with a minimum voltage of 1.6V. The operational amplifier operates correctly at voltages as low as 1.5V. The amplifier power consumption is extremely low, around 8mW, with an optimal quiescent current and minimum current preservation in the output stage.A principal contribuição desta dissertação é a implementação de circuitos integrados de muito baixo consumo e alta eficiência, prontos a ser implementados num circuito de extração de energia com base num elemento piezoelétrico. Esta tese foca-se no desenvolvimento de um circuito de referência de corrente e um amplificador operacional com baixa exigência de consumo. Uma revisão da literatura é realizada, incluindo introdução à tecnologia Complementary Metal-Oxide-Semiconductor (CMOS), e implementação de conhecidos circuitos de baixo consumo. Várias implementações de referência de tensão e corrente são consideradas, e amplificadores operacionais também. Uma referência de corrente auto polarizada com extremo baixo consumo é desenvolvida e verificada. Um amplificador operacional original é proposto com uma topologia de seleção de corrente mínima. Este circuito é constituído por três estágios, com um estágio de saída de classe AB, e um circuito translinear. O circuito tem em consideração redução de ruído na sua implementação. Os circuitos são desenvolvidos com base na tecnologia 0.35mm CMOS. Uma layout foi também desenhada com o propósito de fabricação. A tecnologia foi escolhida tendo em conta o seu custo versus desempenho. A referência de corrente produz uma corrente de 12nA, permanecendo estável para tensões de alimentação de variáveis, com uma tensão mínima de 1.6V. O circuito mostra um coeficiente de temperatura satisfatório. O amplificador operacional funciona com tensão de alimentação mínima de 1.5V, com um consumo baixo de 8mW, com uma corrente mínima mantida no estágio de saída

Tehonhallinta integroidulle hermosignaalin hallintapiirille

Wireless biosignal measurement is a growing opportunity to increase the efficiency of medical procedures: An integrated circuit (receiver) is implanted inside human tissue and it’s output can be read wirelessly with a transmitter that also provides energy for the implant. This method requires RFID technology, where wireless data is transmitted in the RF-band back-and-forth between the receiver and transmitter. The receiver can be implemented either as an active design, where a local power supply is required inside the receiver, or as a passive design without internal energy storage. However, as the modern CMOS process is fairly advanced and the power consumption is low - passive designs are the most common. In the passive design the power for the receiver is drawn from the electromagnetic field transmitted to the chip, generally with electromagnetic induction. A design and implementation of an 860 MHz UHF-band RFID power system is presented in this work and its performance evaluated. The system was designed for a wireless EEG (electroencephalography) reader that can be implanted under the skalp – but the design principles can be expanded upon any RF-band RFID system. The final system works with an input power of -6.8 dBm with a startup time of slightly below 40 µs with specifications of 700 mV to 150 µA load. The LDO line regulation achieves a -51 dB level at DC with the full bandwidth covered. The RF Rectifier uses the design principles of a cross-coupled rectifier and a 63% conversion efficiency is achieved with the proposed matching circuitry. The reference circuitry is designed with the Betamultiplier architecture and expanded slightly to improve the current consumption in the circuit. The reference current is set at 100 nA and reference voltage at 400 mV.Langaton biosignaalien mittaus mahdollistaa yleisien lääketieteellisien signaalien mittauksien tehokkuuden kasvamista: Integroitu elektroninen piiri voidaan asentaa ihmisen kudokseen ja tämän sirun ulosantama tieto voidaan lukea langattomasti lukijalla, mikä useassa tapauksessa toimittaa myös energian sirulle. Tämä teknologia vaatii RFID teknologiaa, mikä on hyvin tunnettu ja tutkittu langattoman datan siirtämiseen kehitelty teknologia radiotaajuuksilla lukijan ja vastaanottimen välillä. Lukija voidaan suunnitella sekä passiiviseksi että aktiiviseksi, mutta modernin CMOS- teknologian tehonkulutus ominaisuuksien vuoksi RFID-lukijat ovat yleisesti passiivisia. Passiivisessa RFID suunnittelussa lukija vastaanottaa tarvitsemansa energian vastaanottimelta yleisesti elektromagneettisen induktion avulla. 860 MHz UHF-kaistan suunnitelu ja toteutus käydään läpi tässä työssä ja suorityskyky on mitattu simulaatioilla. Itse järjestelmä oli alunperin suunniteltu langattomaan EEG-lukijaan (aivosähkökäyrä), minkä pystyisi asentamaan päänahan alle - mutta periaatteet pätevät mihin tahansa RF-kaistan järjestelmään. Lopullinen järjestelmä toimii -6.8 dBm sisääntuloteholla ja käynnistysmisaika on hieman alle 40µs 700 mV ja 150 µA kuormaan. Linjaregulaatio saavuttaa -51 dB arvon alhaisilla taajuuksilla ja regulaatio on koko kaistan kattava. RF-tasasuuntaaja saavuttaa 63 % AC-DC huippu tehonmuutosarvon ehdotetulla impedanssien sovituspiirillä. Referenssipiiri on suunnitellu Betamultiplier-arkkitehtuurilla ja modifioitu pienentämään virrankulutusta. Referenssit ovat 100 nA ja 400 mV

Uma referência de tensão e corrente CMOS utilizando SCCTs e com VDD de 0,85 V

This work presents a topology of a voltage and current reference with little sensitivity in relation to operating temperature, supply voltage and the effects of CMOS fabrication processes. To achieve thermal compensation, a self-cascode composite transistor (SCCT) configuration is used, which is responsible for the generation of PTAT (proportional to absolute temperature) and CTAT (complementary to absolute temperature) voltages, which are summed through the aid of amplifiers operational (AmpOp) and current mirrors. The circuit provides an average voltage and current reference, measured values, of 483.58 mV and 1.317 µA with temperature coefficients (TC) of 25 ppm/°C and 77 ppm/°C respectively, operating in a temperature range from -30 °C to 100 °C, with a minimum voltage of 850 mV and average PSR at 50 Hz, -15.2 dB and -16.36 dB at 1.8 V for VREF and IREF respectively. The developed circuit area is 269 µm x 654 µm. It is presented in this dissertation, the project description, and pertinent simulations of the post-layout circuit of the proposed topology and its electrical characterization. The circuit was developed using a standard 180 nm CMOS process.Este trabalho apresenta uma topologia de uma referência de tensão e corrente pouco sensível em relação à temperatura de operação, tensão de alimentação e aos efeitos dos processos de fabricação CMOS. Para alcançar a compensação térmica, é utilizado uma configuração self-cascode composite transistor (SCCT), que é responsável pela geração das tensões PTAT (proportional to absolute temperature) e CTAT (complementary to absolute temperature), que são somadas através do auxílio de amplificadores operacionais (AmpOp) e espelhos de corrente. O circuito fornece uma referência de tensão e corrente média, dos valores medidos, de 483,58 mV e 1,317 µA com coeficientes de temperatura (TC) de 25 ppm/ °C e 77 ppm/ °C respectivamente, operando em uma faixa de temperatura de -30 °C a 100 °C, com uma tensão mínima de 850 mV e PSR médio, em 50 Hz, de -15,2 dB e -16,36 dB em 1.8 V para VREF e IREF respectivamente. A área do circuito desenvolvido é 269 µm x 654 µm. São apresentadas nesta dissertação, a descrição do projeto, e simulações pertinentes do circuito pós leiaute da topologia proposta e sua caracterização elétrica. O circuito foi desenvolvido usando um processo CMOS padrão de 180 nm

Analogue micropower FET techniques review

A detailed introduction to published analogue circuit design techniques using Si and Si/SiGe FET devices for very low-power applications is presented in this review. The topics discussed include sub-threshold operation in FET devices, micro-current mirrors and cascode techniques, voltage level-shifting and class-AB operation, the bulk-drive approach, the floating-gate method, micropower transconductance-capacitance and log-domain filters and strained-channel FET technologies

CMOS Integrated Circuits for RF-powered Wireless Temperature Sensor

This dissertation presents original research contributions in the form of twelve scientific publications that represent advances related to RF-to-DC converters, reference circuits (voltage, current and frequency) and temperature sensors. The primary focus of this research was to design efficient and low power CMOS-based circuit components, which are useful in various blocks of an RF-powered wireless sensor node.  The RF-to-DC converter or rectifier converts RF energy into DC energy, which is utilized by the sensor node. In the implementation of a CMOS-based RF-to-DC converter, the threshold voltage of MOS transistors mainly affects the conversion efficiency. Hence, for the first part of this research, different threshold voltage compensation schemes were developed for the rectifiers. These schemes were divided into two parts; first, the use of the MOSFET body terminal biasing technique and second, the use of an auxiliary circuit to obtain threshold voltage compensation. In addition to these schemes, the use of an alternate signaling scheme for voltage multiplier configuration of differential input RF-harvesters has also been investigated.  A known absolute value of voltage or current is the most useful for an integrated circuit. Thus, the circuit which generates the absolute value of voltage or current is cited as the voltage or current reference circuit respectively. Hence, in the second part of the research, simple, low power and moderately accurate, voltage and current reference circuits were developed for the power management unit of the sensor node. Besides voltage and current reference circuits, a frequency reference circuit was also designed. The use of the frequency reference circuit is in the digital processing and timing functions of the sensor node.  In the final part of the research, temperature sensing was selected as an application for the sensor node. Here, voltage and current based sensor cores were developed to sense the temperature. A smart temperature sensor was designed by using the voltage cores to obtain temperature information in terms of the duty-cycle. Similarly, the temperature equivalent current was converted into the frequency to obtain a temperature equivalent output signal.  All these implementations were done by using two integrated circuits which were fabricated during the year 2013-14.

Wide bandgap semiconductor radiation detectors for future space applications

SiC and Al0.52In0.48P photodiodes were experimentally investigated for their suitability as radiation detectors for use in high temperature (≥ 20 °C) environments applications. Commercial-off-the-shelf (COTS) 4H-SiC UV p-n photodiodes were repurposed for use as X-ray detectors. Custom-made Al0.52In0.48P p+-i-n+ mesa X-ray photodiodes were also studied. The measurements used an 55Fe radioisotope X-ray source. The electrical characterisation of the commercial 4H-SiC UV p-n photodiodes and the Al0.52In0.48P p+-i-n+ mesa X-ray photodiodes were investigated at temperatures up to 140 °C and 100 °C, respectively. The photocurrent of the commercial 4H-SiC UV p-n photodiodes were also investigated at temperatures up to 80 °C. The temperature dependences of the energy resolution (FWHM at 5.9 keV) of photon counting spectrometers employing these two different kinds of photodiodes are reported, along with shaping time noise analysis. One of the commercial 4H-SiC UV p-n photodiodes was subsequently characterised under illumination from X-rays of energy 4.95 keV to 21.17 keV, generated by fluorescing high purity metal foils with X-rays from a Mo target X-ray tube. These measurements were conducted at a temperature of 33 °C. The investigation included measurements of spectrometer energy resolution, energy response linearity, and flux linearity measurements. One of the commercial 4H-SiC UV p-n photodiodes was further studied as a direct electron detector of soft (< 66 keV) electrons (β- particles) at temperatures up to 100 °C. In addition to experimental measurements, Monte Carlo simulations were conducted and compared with the spectrometer’s response. Results of the research presented in this thesis indicates the commercial 4H-SiC UV photodiodes and the Al0.52In0.48P X-ray photodiodes can be used for high temperature X-rays spectroscopy. Moreover, the results also show that the commercial 4H-SiC UV photodiode can be used for high temperature electron spectroscopy. The work with the 4H-SiC UV photodiodes shows that they can be repurposed for use in low cost X-ray spectroscopy missions, such as CubeSat instrumentation to monitor solar X-rays. The work with the Al0.52In0.48P X-ray photodiodes shows the current state of the art of custom compound semiconductor X-ray detectors specifically designed for such environments

Analogue micropower FET techniques review

Accepted versio