Particle Swarm Optimization Algorithm for Leakage Power Reduction in VLSI Circuits

 Leakage power is the dominant source of power dissipation innanometer technology. As per the International Technology Roadmap forSemiconductors (ITRS) static power dominates dynamic power with theadvancement in technology. One of the well-known techniques used forleakage reduction is Input Vector Control (IVC). Due to stacking effect inIVC, it gives less leakage for the Minimum Leakage Vector (MLV) appliedat inputs of test circuit. This paper introduces Particle Swarm Optimization(PSO) algorithm to the field of VLSI to find minimum leakage vector.Another optimization algorithm called Genetic algorithm (GA) is alsoimplemented to search MLV and compared with PSO in terms of number ofiterations. The proposed approach is validated by simulating few testcircuits. Both GA and PSO algorithms are implemented in Verilog HDLand the simulations are carried out using Xilinx 9.2i. From the simulationresults it is found that PSO based approach is best in finding MLVcompared to Genetic based implementation as PSO technique uses lessruntime compared to GA. To the best of the author’s knowledge PSOalgorithm is used in IVC technique to optimize power for the first time andit is quite successful in searching MLV

Physical design algorithms for asynchronous circuits

Asynchronous designs have been demonstrated to be able to achieve both higher performance and lower power compared with their synchronous counterparts. It provides a very promising solution to the emerging challenges in advanced technology. However, due to the lack of proper EDA tool support, the design cycle for asynchronous circuits is much longer compared with the one for synchronous circuits. Thus, even with many advantages, asynchronous circuits are still not the mainstream in the industry. In this thesis, we provides several algorithms to resolve the emerging issues for the physical design of asynchronous circuits. Our proposed algorithms optimize asynchronous circuits using placement, gate sizing, repeater insertion and pipeline buffer insertion techniques. An incremental maximum cycle ratio algorithm is also proposed to speed up the timing analysis of asynchronous circuits

Enhancing Power Efficient Design Techniques in Deep Submicron Era

Excessive power dissipation has been one of the major bottlenecks for design and manufacture in the past couple of decades. Power efficient design has become more and more challenging when technology scales down to the deep submicron era that features the dominance of leakage, the manufacture variation, the on-chip temperature variation and higher reliability requirements, among others. Most of the computer aided design (CAD) tools and algorithms currently used in industry were developed in the pre deep submicron era and did not consider the new features explicitly and adequately. Recent research advances in deep submicron design, such as the mechanisms of leakage, the source and characterization of manufacture variation, the cause and models of on-chip temperature variation, provide us the opportunity to incorporate these important issues in power efficient design. We explore this opportunity in this dissertation by demonstrating that significant power reduction can be achieved with only minor modification to the existing CAD tools and algorithms. First, we consider peak current, which has become critical for circuit's reliability in deep submicron design. Traditional low power design techniques focus on the reduction of average power. We propose to reduce peak current while keeping the overhead on average power as small as possible. Second, dual Vt technique and gate sizing have been used simultaneously for leakage savings. However, this approach becomes less effective in deep submicron design. We propose to use the newly developed process-induced mechanical stress to enhance its performance. Finally, in deep submicron design, the impact of on-chip temperature variation on leakage and performance becomes more and more significant. We propose a temperature-aware dual Vt approach to alleviate hot spots and achieve further leakage reduction. We also consider this leakage-temperature dependency in the dynamic voltage scaling approach and discover that a commonly accepted result is incorrect for the current technology. We conduct extensive experiments with popular design benchmarks, using the latest industry CAD tools and design libraries. The results show that our proposed enhancements are promising in power saving and are practical to solve the low power design challenges in deep submicron era

Multi-objective Pareto front and particle swarm optimization algorithms for power dissipation reduction in microprocessors

The progress of microelectronics making possible higher integration densities, and a considerable development of on-board systems are currently undergoing, this growth comes up against a limiting factor of power dissipation. Higher power dissipation will cause an immediate spread of generated heat which causes thermal problems. Consequently, the system's total consumed energy will increase as the system temperature increase. High temperatures in microprocessors and large thermal energy of computer systems produce huge problems of system confidence, performance, and cooling expenses. Power consumed by processors are mainly due to the increase in number of cores and the clock frequency, which is dissipated in the form of heat and causes thermal challenges for chip designers. As the microprocessor’s performance has increased remarkably in Nano-meter technology, power dissipation is becoming non-negligible. To solve this problem, this article addresses power dissipation reduction issues for high performance processors using multi-objective Pareto front (PF), and particle swarm optimization (PSO) algorithms to achieve power dissipation as a prior computation that reduces the real delay of a target microprocessor unit. Simulation is verified the conceptual fundamentals and optimization of joint body and supply voltages (Vth-VDD) which showing satisfactory findings

Diagnosis of induction machines by parameter estimation

International audienceThe type of control system used for electrical machines depends on the use (nature of the load, operating states, etc.) to which the machine will be put. The precise type of use determines the control laws which apply. Mechanics are also very important because they affect performance. Another factor of essential importance in industrial applications is operating safety. Finally, the problem of how to control a number of different machines, whose interactions and outputs must be coordinated, is addressed and solutions are presented. These and other issues are addressed here by a range of expert contributors, each of whom are specialists in their particular field. This book is primarily aimed at those involved in complex systems design, but engineers in a range of related fields such as electrical engineering, instrumentation and control, and industrial engineering, will also find this a useful source of information

Design Space Re-Engineering for Power Minimization in Modern Embedded Systems

Power minimization is a critical challenge for modern embedded system design. Recently, due to the rapid increase of system's complexity and the power density, there is a growing need for power control techniques at various design levels. Meanwhile, due to technology scaling, leakage power has become a significant part of power dissipation in the CMOS circuits and new techniques are needed to reduce leakage power. As a result, many new power minimization techniques have been proposed such as voltage island, gate sizing, multiple supply and threshold voltage, power gating and input vector control, etc. These design options further enlarge the design space and make it prohibitively expensive to explore for the most energy efficient design solution. Consequently, heuristic algorithms and randomized algorithms are frequently used to explore the design space, seeking sub-optimal solutions to meet the time-to-market requirements. These algorithms are based on the idea of truncating the design space and restricting the search in a subset of the original design space. While this approach can effectively reduce the runtime of searching, it may also exclude high-quality design solutions and cause design quality degradation. When the solution to one problem is used as the base for another problem, such solution quality degradation will accumulate. In modern electronics system design, when several such algorithms are used in series to solve problems in different design levels, the final solution can be far off the optimal one. In my Ph.D. work, I develop a {\em re-engineering} methodology to facilitate exploring the design space of power efficient embedded systems design. The direct goal is to enhance the performance of existing low power techniques. The methodology is based on the idea that design quality can be improved via iterative ``re-shaping'' the design space based on the ``bad'' structure in the obtained design solutions; the searching run-time can be reduced by the guidance from previous exploration. This approach can be described in three phases: (1) apply the existing techniques to obtain a sub-optimal solution; (2) analyze the solution and expand the design space accordingly; and (3) re-apply the technique to re-explore the enlarged design space. We apply this methodology at different levels of embedded system design to minimize power: (i) switching power reduction in sequential logic synthesis; (ii) gate-level static leakage current reduction; (iii) dual threshold voltage CMOS circuits design; and (iv) system-level energy-efficient detection scheme for wireless sensor networks. An extensive amount of experiments have been conducted and the results have shown that this methodology can effectively enhance the power efficiency of the existing embedded system design flows with very little overhead

EMC in Power Electronics and PCB Design

This dissertation consists of two parts. Part I is about Electromagnetic Compatibility (EMC) in power electronics and part II is about the Maximum Radiated Electromagnetic Emissions Calculator (MREMC), which is a software tool for EMC in printed circuit board (PCB) design. Switched-mode power converters can be significant sources of electromagnetic fields that interfere with the proper operation of nearby circuits or distant radio receivers. Part I of this dissertation provides comprehensive and organized information on the latest EMC developments in power converters. It describes and evaluates different technologies to ensure that power converters meet electromagnetic compatibility requirements. Chapters 2 and 3 describe EMC noise sources and coupling mechanisms in power converters. Chapter 4 reviews the measurements used to characterize and troubleshoot EMC problems. Chapters 5 - 8 cover passive filter solutions, active filter solutions, noise cancellation methods and reduced-noise driving schemes. Part II describes the methods used, calculations made, and implementation details of the MREMC, which is a software tool that allows the user to calculate the maximum possible radiated emissions that could occur due to specific source geometries on a PCB. Chapters 9 - 13 covers the I/O coupling EMI algorithm, Common-mode EMI algorithm, Power Bus EMI algorithm and Differential-Mode EMI algorithm used in the MREMC