A proof-of-concept superregenerative QPSK transceiver

In this paper we present a description and experimental verification of an HF-band proof-of-concept superregenerative transceiver for QPSK signals. We describe a simple implementation of an all-digital, FPGA-based, QPSK transmitter section. On the receiver side, the quench signal is generated in the same FPGA with a minimum of analog circuitry. As the main novelty, we present a simple synchronization scheme suitable for packetized transmissions.Peer ReviewedPostprint (author’s final draft

의료용 인체 삽입물을 위한 무선 저전력 송수신기에 관한 연구

학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2016. 2. 남상욱.This thesis presents the wireless transceiver for medical implant application. The high propagation loss in human body which has high relative permittivity and conductive makes the implantable device be required for high sensitivity. Moreover, the device should have low power consumption to use for wireless implant medical application due to a restricted battery life. Also, this problem should be solved for on-body device considering integration with mobile device in the future. Simultaneously, the specific medical application such as epiretinal prosthesis, multi-channel electroencephalogram sensor demand high-data rate. Therefore, it is a main challenge that enhancing the devices power consumption and data-rate for implantable medical application. In order to enhance the performance of the device, several techniques are proposed in implantable human body transceivers. Firstly, the propagation loss in human-body is calculated for determine the frequency for medical implant application. The frequency bands allocated by FCC or MICS are too narrow and high lossy bands in human-body. For this reason, the optimum frequency for Implantable medical device is found by using Frisss formula and the link budget is calculated for capsule endoscopy system. The optimum frequency is verified through image recovery experiment in liquid human phantom and pig by using designed capsule endoscopy system. Secondly, the Super-Regenerative Receiver (SRR) with Digital Self-Quenching Loop (DSQL) is proposed for low power consumption. The proposed DSQL replaces the envelope detector used in a conventional SRR and minimizes power consumption by generating a self-quench signal digitally for a super-regenerative oscillator. The measurement results are given to show the performance of the proposed receiver. Thirdly, the RF Current Reused and Current Combining (CRCC) Power Amplifier (PA) is proposed for low power and high-speed transmitter. Normally, the PA having low output power has a feasibility issue that an optimum impedance of PA is too high to match with antenna impedance. For this reason, obtaining the maximum efficiency of PA is difficult for conventional structure. Moreover, conventional PAs output bandwidth is to be narrow due to high impedance transform ratio between PAs output and antennas input impedances. The CRCC structure solves this issue by decreasing the impedance transform ratio. The transmitter with CRCC PA is designed and verified through the measurement.Chapter 1. Introduction 1 1.1. WBAN (Wireless Body Area Network) 1 1.2. Challenges in Designing Transceiver for Medical Implant Application 7 Chapter 2. Propagation Loss in Human Body 10 2.1. Introduction 10 2.2. Far field approximation in human-body 13 2.3. Calculation of propagation loss in human-body 15 2.3.1. Frisss formula 15 2.3.2. Efficiency of transmitting antenna in human-body 17 2.4. Calculation of propagation loss in human-body and conclusion 19 Chapter 3. A Design of Transceiver for Capsule Endoscopy Application 21 3.1. Introduction 21 3.2. System Link Budget Calculation 24 3.3. Implementation 26 3.3.1. Transmitter with class B amplifier 26 3.3.2. Super-heterodyne receiver with AGC 28 3.3.3. Measurement results 30 3.4. Image recovery experiment 35 3.4.1. Integration of capsule endoscopy 35 3.4.2. Image recovery in the liquid human phantom 38 3.4.3. Image recovery in a pigs stomach and large intestine 40 3.5. Conclusion 41 Chapter 4. Super-Regenerative Receiver with Digitally Self-Quenching Loop 42 4.1. Introduction 42 4.1.1. Selection of receivers architecture for implantable medical device 44 4.1.2. Previous study of super-regenerative receiver 50 4.2. Main idea of proposed super-regenerative receiver 51 4.3. Description of proposed receiver 53 4.3.1. Digital self-quenching loop 55 4.3.2. Low noise amplifier and super-regenerative oscillator 57 4.3.3. Active RC filter for low power consumption 59 4.4. Experimental results 63 4.5. Summary and conclusion 69 Chapter 5. A Transmitter with Current-Reused and Current-Combining PA 71 5.1. Introduction 71 5.1.1. Previous study of OOK transmitter 72 5.2. Main idea of proposed transmitter 73 5.3. Description of proposed transmitter 79 5.3.1. Current-combining and current-reused PA 79 5.3.2. Ring oscillator with driving buffer 83 5.4. Experimental Results 85 5.5. Summary and conclusion 93 Chapter 6. Conclusion 95 Chapter 7. Appendix 97 7.1. Output spectrum of OOK signal 97 7.2. Theoretical BER of OOK comunication 99 Bibliography 101 초 록 109Docto

Ultra-low-energy transmitters for battery-free wireless sensor networks

As the number of autonomous data collection applications keep increasing, the demand for wireless sensor networks (WSNs) has seen explosive growth. In this dissertation, an ultra-low-energy WSN transmitter is developed to reduce the energy consumption of sensor nodes in WSNs. With an ultra-low-energy transceiver, it is possible to eliminate the battery in the sensor node and power itself with an energy harvester, thus creating a battery-free sensor node. A variety of applications can be accommodated with the battery-free sensor node as it has small size, light weight, and endless lifetime. Two prototype WSN transmitters are implemented to demonstrate the transmitter energy minimization. The first transmitter incorporates a fast frequency calibration to shorten the oscillation frequency tuning time. This minimizes energy wasted during the transmitter start-up period. The energy consumption of the second transmitter that employs a power oscillator architecture is minimized by maximizing the transmitter efficiency. The efficiency of the power oscillator circuit is analyzed and the design procedure for maximum efficiency is then developed. Prototype WSN transmitters were fabricated in 0.18-um CMOS technology. The first transmitter operates in the 915-MHz ISM band. With 0.5-MHz reference frequency, the transmitter takes only 72 us for the BFSK frequency calibration. It dissipates a power of 1.91 mW while radiating a power of -2.9 dBm. The second transmitter operates in the 2.45-GHz ISM band on a single supply of 0.65 V. The transmitter has efficiency as high as 23 % at -5.2 dBm radiated power. This corresponds to a low power consumption of 1.34 mW

Integrated Circuit and System Design for Cognitive Radio and Ultra-Low Power Applications

The ubiquitous presence of wireless and battery-powered devices is an inseparable and invincible feature of our modern life. Meanwhile, the spectrum aggregation, and limited battery capacity of handheld devices challenge the exploding demand and growth of such radio systems. In this work, we try to present two separate solutions for each case; an ultra-wideband (UWB) receiver for Cognitive Radio (CR) applications to deal with spectrum aggregation, and an ultra-low power (ULP) receiver to enhance battery life of handheld wireless devices. Limited linearity and LO harmonics mixing are two major issues that ultra-wideband receivers, and CR in particular, are dealing with. Direct conversion schemes, based on current-driven passive mixers, have shown to improve the linearity, but unable to resolve LO harmonic mixing problem. They are usually limited to 3rd, and 5th harmonics rejection or require very complex and power hungry circuitry for higher number of harmonics. This work presents a heterodyne up-down conversion scheme in 180 nm CMOS technology for CR applications (54-862 MHz band) that mitigates the harmonic mixing issue for all the harmonics, while by employing an active feedback loop, a comparable to the state-of-the art IIP3 of better than +10 dBm is achieved. Measurements show an average NF of 7.5 dB when the active feedback loop is off (i.e. in the absence of destructive interference), and 15.5 dB when the feedback loop is active and a 0 dBm interferer is applied, respectively. Also, the second part of this work presents an ultra-low power super-regenerative receiver (SRR) suitable for OOK modulation and provides analytical insight into its design procedure. The receiver is fabricated in 40 nm CMOS technology and operates in the ISM band of 902-928 MHz. Binary search algorithm through Successive Approximation Register (SAR) architecture is being exploited to calibrate the internally generated quench signal and the working frequency of the receiver. Employing an on-chip inductor and a single-ended to differential architecture for the input amplifier has made the receiver fully integrable, eliminating the need for external components. A power consumption of 320 µW from a 0.65 V supply results in an excellent energy efficiency of 80 pJ/b at 4 Mb/s data rate. The receiver also employs an ADC that enables soft-decisioning and a convenient sensitivity-data rate trade-off, achieving sensitivity of -86.5, and -101.5 dBm at 1000 and 31.25 kbps data rate, respectivel

Integrated Circuit and System Design for Cognitive Radio and Ultra-Low Power Applications

The ubiquitous presence of wireless and battery-powered devices is an inseparable and invincible feature of our modern life. Meanwhile, the spectrum aggregation, and limited battery capacity of handheld devices challenge the exploding demand and growth of such radio systems. In this work, we try to present two separate solutions for each case; an ultra-wideband (UWB) receiver for Cognitive Radio (CR) applications to deal with spectrum aggregation, and an ultra-low power (ULP) receiver to enhance battery life of handheld wireless devices. Limited linearity and LO harmonics mixing are two major issues that ultra-wideband receivers, and CR in particular, are dealing with. Direct conversion schemes, based on current-driven passive mixers, have shown to improve the linearity, but unable to resolve LO harmonic mixing problem. They are usually limited to 3rd, and 5th harmonics rejection or require very complex and power hungry circuitry for higher number of harmonics. This work presents a heterodyne up-down conversion scheme in 180 nm CMOS technology for CR applications (54-862 MHz band) that mitigates the harmonic mixing issue for all the harmonics, while by employing an active feedback loop, a comparable to the state-of-the art IIP3 of better than +10 dBm is achieved. Measurements show an average NF of 7.5 dB when the active feedback loop is off (i.e. in the absence of destructive interference), and 15.5 dB when the feedback loop is active and a 0 dBm interferer is applied, respectively. Also, the second part of this work presents an ultra-low power super-regenerative receiver (SRR) suitable for OOK modulation and provides analytical insight into its design procedure. The receiver is fabricated in 40 nm CMOS technology and operates in the ISM band of 902-928 MHz. Binary search algorithm through Successive Approximation Register (SAR) architecture is being exploited to calibrate the internally generated quench signal and the working frequency of the receiver. Employing an on-chip inductor and a single-ended to differential architecture for the input amplifier has made the receiver fully integrable, eliminating the need for external components. A power consumption of 320 µW from a 0.65 V supply results in an excellent energy efficiency of 80 pJ/b at 4 Mb/s data rate. The receiver also employs an ADC that enables soft-decisioning and a convenient sensitivity-data rate trade-off, achieving sensitivity of -86.5, and -101.5 dBm at 1000 and 31.25 kbps data rate, respectivel

Signal-Processing-Driven Integrated Circuits for Energy Constrained Microsystems.

The exponential growth in IC technology has enabled low-cost and increasingly capable wireless sensor nodes which provide a promising way forward to realize the vision of a trillion connected sensors in the next decade. However there are still many design challenges ahead to make these sensor nodes small,low-cost,secure,reliable and energy-efficient to name a few. Since the wireless nodes are expected to operate on a limited energy source or in some cases on harvested energy, the energy consumption of each building block is of prime importance to prolong the life of a sensor node. It has been found that the radio communication when active has been one of the highest power consuming modules on a sensor node. Low-energy protocols, e.g. processing the raw sensor data on-node, are more energy efficient for some applications as compared to transmitting the raw data over a wireless channel to a cloud server. In this thesis we explore signal processing techniques to realize a low power radio solution for wireless communication. Two prototype chips have been designed and their performance has been evaluated. The first prototype chip exploits compressed sensing for Ultra-Wide-Band (UWB) communication. UWB signals typically require a high ADC sampling rate in the receiver which results in high power consumption. Compressed sensing is demonstrated to relax the ADC sampling rate to save power. The second prototype chip exploits the sensitivity vs. power trade-off in a radio receiver to achieve iso-performance at lower power consumption and the time-varying wireless channel characteristics are used to adapt the sampling frequency of the receiver based on the SNR/Link quality of the communication channel, saving power, while maintaining the desired system performance. It is envisioned that embedded machine learning will play a key role in the integration of sensory data with prior knowledge for distributed intelligent sensing which might enable reduced wireless network traffic to a cloud server. A Near-Threshold hardware accelerator for arbitrary Bayesian network was designed for clique-tree message passing algorithm used for probabilistic inference. The hardware accelerator was benchmarked by the mid-size ALARM Bayesian network with total energy consumption of 76nJ for 250µS execution time.PhDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/107130/1/oukhan_1.pd

Low power receivers for wireless sensor networks

Wireless sensor networks are becoming important in several monitoring and sensing applications. Ultra low power consumption in the sensor nodes is important for extending the battery life of the nodes. In this dissertation, two low power BFSK receiver architectures are proposed and verified with prototype implementations in silicion. A 2.4 GHz 1 Mb/s polyphase filter (PPF) BFSK receiver demonstrates ±180 ppm frequency offset tolerance (FOT) and 40 dB adjacent channel rejection (ACR) at a modulation index (MI) of 2, with a power consumption of 1.9 mW. High FOT at low MI is achieved by a frequency-to-energy conversion architecture using PPFs without any frequency correction. The proposed hybrid topology of the PPF provides an improved ACR at reduced power. To further improve the energy efficiency, a low energy 900 MHz mixer-less BFSK receiver is designed. High gain frequency-to-amplitude conversion and better sensitivity is achieved by a linear amplifier with Q-enhanced LC tank, eliminating the need for local oscillators and mixers. With a power consumption of 500 μW, the receiver achieves sensitivities of -90 dBm and -76 dBm for data rates of 0.5 Mb/s and 6 Mb/s, respectively. The energy efficiency is 80 pJ/b when operating at 6 Mb/s

Energy Aware RF Transceiver for Wireless Body Area Networks (WBAN)

Ph.DDOCTOR OF PHILOSOPH

Energy-Efficient Wake-up Receivers for 915-MHz ISM Band Applications

Wake-up receiver (WuRx) is a well-known approach for optimizing the latency and power consumption of ultra-low power transceivers in wireless sensor nodes. Tuned RF (TRF) or Envelope Detection architecture is an appropriate topology for short-range Wireless Body Area Network (WBAN) applications, where achieving a very high sensitivity is not a priority. However, the demand for an improved sensitivity gets emphasized for longer transmission ranges. Regardless of the application, considering the existing trade-off between the power and sensitivity, design techniques and novel architectures are usually employed to optimize the power-sensitivity product. Moreover, considering the negative impact of higher data rate on the sensitivity, the energy-sensitivity product can be a more reasonable figure of merit when comparing WuRx designs. In this thesis, the RF-subsampling architecture has been combined with the TRF receiver architecture as a first approach for improving the power-sensitivity product. The overall power consumption is reduced as a result of employing the subsampling topology with a low-frequency local oscillator (LO). Post layout simulations show that the proposed WuRx draws only 56 μA from a 0.5 V supply and exhibits an input sensitivity of -70 dBm for a data rate of 100 kbps. The chip occupies an area of 0.15 mm2 and is fabricated with TSMC 90nm CMOS technology. Another major contribution of this work is to propose and implement a novel dual-mode ultra-low-power WuRx based on the subsampling topology, which not only reduces the overall power consumption but also optimizes the energy-sensitivity product of the receiver. During the typical mode of operation known as the Monitoring (MO) mode, the start frame bits are received at a rate of as low as 10 kbps. Having received the true preamble bits in the MO mode, the remaining wake-up pattern bits are received at a higher rate of 200 kbps during the Identifier (ID) mode. By lowering the gain of the front-end amplifier in the MO mode, the power dissipation is reduced, which in turn causes an increase in the overall noise figure of the receiver. However, adequate sensitivity and hence an optimized energy-sensitivity product is maintained by intentionally lowering the data rate as well as the detection bandwidth of the receiver in the MO mode. The proposed wake-up receiver has been designed and fabricated in IBM 130 nm technology with a core size of about 0.2 mm2 for the target frequency range of 902-928 MHz. The measured results show that the proposed dual-mode receiver achieves a sensitivity of -78.5 dBm and -75 dBm while dissipating an average power of 16.4 µW and 22.9 µW during MO and ID modes, respectively