Engine performance characteristics and evaluation of variation in the length of intake plenum

In the engine with multipoint fuel injection system using electronically controlled fuel injectors has an intake manifold in which only the air flows and, the fuel is injected into the intake valve. Since the intake manifolds transport mainly air, the supercharging effects of the variable length intake plenum will be different from carbureted engine. Engine tests have been carried out with the aim of constituting a base study to design a new variable length intake manifold plenum. The objective in this research is to study the engine performance characteristics and to evaluate the effects of the variation in the length of intake plenum. The engine test bed used for experimental work consists of a control panel, a hydraulic dynamometer and measurement instruments to measure the parameters of engine performance characteristics. The control panel is being used to perform administrative and management operating system. Besides that, the hydraulic dynamometer was used to measure the power of an engine by using a cell filled with liquid to increase its load. Thus, measurement instrument is provided in this test to measure the as brake torque, brake power, thermal efficiency and specific fuel consumption. The results showed that the variation in the plenum length causes an improvement on the engine performance characteristics especially on the fuel consumption at high load and low engine speeds which are put forward the system using for urban roads. From this experiment, it will show the behavior of engine performance

Quarc: a novel network-on-chip architecture

This paper introduces the Quarc NoC, a novel NoC architecture inspired by the Spidergon NoC. The Quarc scheme significantly outperforms the Spidergon NoC through balancing the traffic which is the result of the modifications applied to the topology and the routing elements.The proposed architecture is highly efficient in performing collective communication operations including broadcast and multicast. We present the topology, routing discipline and switch architecture for the Quarc NoC and demonstrate the performance with the results obtained from discrete event simulations

Adaptive Wireless Networking

This paper presents the Adaptive Wireless Networking (AWGN) project. The project aims to develop methods and technologies that can be used to design efficient adaptable and reconfigurable mobile terminals for future wireless communication systems. An overview of the activities in the project is given. Furthermore our vision on adaptivity in wireless communications and suggestions for future activities are presented

Quarc: a high-efficiency network on-chip architecture

The novel Quarc NoC architecture, inspired by the Spidergon scheme is introduced as a NoC architecture that is highly efficient in performing collective communication operations including broadcast and multicast. The efficiency of the Quarc architecture is achieved through balancing the traffic which is the result of the modifications applied to the topology and the routing elements of the Spidergon NoC. This paper provides an ASIC implementation of both architectures using UMCpsilas 0.13 mum CMOS technology and demonstrates an analysis and comparison of the cost and performance between the Quarc and the Spidergon NoCs

Design and implementation of the Quarc network on-chip

Networks-on-Chip (NoC) have emerged as alternative to buses to provide a packet-switched communication medium for modular development of large Systems-on-Chip. However, to successfully replace its predecessor, the NoC has to be able to efficiently exchange all types of traffic including collective communications. The latter is especially important for e.g. cache updates in multicore systems. The Quarc NoC architecture has been introduced as a Networks-on-Chip which is highly efficient in exchanging all types of traffic including broadcast and multicast. In this paper we present the hardware implementation of the switch architecture and the network adapter (transceiver) of the Quarc NoC. Moreover, the paper presents an analysis and comparison of the cost and performance between the Quarc and the Spidergon NoCs implemented in Verilog targeting the Xilinx Virtex FPGA family. We demonstrate a dramatic improvement in performance over the Spidergon especially for broadcast traffic, at no additional hardware cost