A FPGA based Steganographic System Implementing a Modern Steganalysis Resistant LSB Algorithm

Steganography differs from other data hiding techniques because it encodes secret message inside cover object in such a way that transmission of secret message also remains a secret. Widespread usage of digital images, lower computational complexity and better performance makes spatial domain steganographic algorithms well suited for hardware implementation, which are not very frequent. This work tries to implement a modern steganalysis resistant LSB algorithm on FPGA based hardware. The presented work also optimises various operations and elements from original one third probability algorithm with respect to hardware implementation. The target FPGA for the implementation is Xilinx SP605 board (Spartan 6 series XC6SLX45T FPGA). Stego images obtained by the implementation have been thoroughly examined for various qualitative and quantitative aspects, which are found to be at par with original algorithm

06141 Abstracts Collection -- Dynamically Reconfigurable Architectures

From 02.04.06 to 07.04.06, the Dagstuhl Seminar 06141 ``Dynamically Reconfigurable Architectures\u27\u27 was held in the International Conference and Research Center (IBFI), Schloss Dagstuhl. During the seminar, several participants presented their current research, and ongoing work and open problems were discussed. Abstracts of the presentations given during the seminar as well as abstracts of seminar results and ideas are put together in this paper. The first section describes the seminar topics and goals in general. Links to extended abstracts or full papers are provided, if available

Reconfigurable hardware architecture of public key crypto processor for VANET and wireless sensor nodes

This work proposes encryption of text and image data, embedding as elliptic curve point. Finite field arithmetic is utilised efficiently in this reconfigurable crypto system. Pre-computations for text data and image input conversion is done using MATLAB. This architecture is tailored for cryptographic applications and VANET using Xilinx Spartan-xc3s100e-4-fg320 FPGA with Verilog coding. Total encryption and decryption time results around 10.09021 microseconds for 100×100 images, 22.091 microseconds for 256×256 images and 0.029 microseconds for a message. The message size is varied with different stream size and dynamic mapping of input data and a cipher image with high randomness indicates good security i.e., less vulnerable to attacks. An entropy statistical analysis is performed on plain and encrypted images to assess the strength of the proposed method. An encryption throughput rate is 450 Mbps

Using Quaternion Fourier Transform in Steganography Systems

steganography is the discipline of exchanging information messages in such way that no one, other than the intended recipient, suspects the existence of the message.  The transmitted message can be in textual or multimedia form (audio, image or video) and can be hidden within cover media. Moreover, the hidden message can be in either plain or cipher form.  In steganography, the majority of hiding techniques are implemented either in spatial domain or in frequency domain of the cover media.   The current contribution introduces a new a steganography technique for hiding a textual message within a cover image.   Both the message and the cover image is converted to quaternion form and then only the quaternion message is converted to the frequency domain using Quaternion Fast Fourier Discrete Transform (QFFDT) technique.  Simple quaternion mathematics are used to combine the message (in quaternion frequency domain) within the cover image (in quaternion form).  Conversely, the hidden message can be revealed at the receiver using simple quaternion mathematics in presence of the original cover image.  The proposed method allows hiding a huge amount of data and it is much complicated against steganalysis compared to the traditional methods. The method is assessed using the known performance metrics and the obtained results show that it is robust and more secure against steganalysis attacks without affecting the consumed bandwidth of the communication channel

Hiding text in speech signal using K-means, LSB techniques and chaotic maps

In this paper, a new technique that hides a secret text inside a speech signal without any apparent noise is presented. The technique for encoding the secret text is through first scrambling the text using Chaotic Map, then encoding the scraped text using the Zaslavsky map, and finally hiding the text by breaking the speech signal into blocks and using only half of each block with the LSB, K-means algorithms. The measures (SNR, PSNR, Correlation, SSIM, and MSE) are used on various speech files (“.WAV”), and various secret texts. We observed that the suggested technique offers high security (SNR, PSNR, Correlation, and SSIM) of an encrypted text with low error (MSE). This indicates that the noise level in the speech signal is very low and the speech purity is high, so the suggested method is effective for embedding encrypted text into speech files

PIRANHA: an engine for a methodology of detecting covert communication via image-based steganography

In current cutting-edge steganalysis research, model-building and machine learning has been utilized to detect steganography. However, these models are computationally and cognitively cumbersome, and are specifically and exactly targeted to attack one and only one type of steganography. The model built and utilized in this thesis has shown capability in detecting a class or family of steganography, while also demonstrating that it is viable to construct a minimalist model for steganalysis. The notion of detecting steganographic primitives or families is one that has not been discussed in literature, and would serve well as a first-pass steganographic detection methodology. The model built here serves this end well, and it must be kept in mind that the model presented is posited to work as a front-end broad-pass filter for some of the more computationally advanced and directed stganalytic algorithms currently in use. This thesis attempts to convey a view of steganography and steganalysis in a manner more utilitarian and immediately useful to everyday scenarios. This is vastly different from a good many publications that treat the topic as one relegated only to cloak-and-dagger information passing. The subsequent view of steganography as primarily a communications tool useable by petty information brokers and the like directs the text and helps ensure that the notion of steganography as a digital dead-drop box is abandoned in favor of a more grounded approach. As such, the model presented underperforms specialized models that have been presented in current literature, but also makes use of a large image sample space (747 images) as well as images that are contextually diverse and representative of those seen in wide use. In future applications by either law-enforcement or corporate officials, it is hoped that the model presented in this thesis can aid in rapid and targeted responses without causing undue strain upon an eventual human operator. As such, a design constraint that was utilized for this research favored a False Negative as opposed to a False Positive - this methodology helps to ensure that, in the event of an alert, it is worthwhile to apply a more directed attack against the flagged image

Physical Layer Watermarking of Direct Sequence Spread Spectrum Signals

Security services and mechanisms in wireless networks have long been studied and developed. However, compared to upper network layers, physical layer security did not play a signicant role in the OSI security model. Thanks to the easier implementation and verication methods brought by the development of software dened radio (SDR) techniques, physical layer security mechanisms have recently drawn increasing interest from researchers. Digital watermarking is one of the popular security techniques that can fully utilize various exclusive characteristics of the physical layer. This thesis proposes a physical layer watermarking technique named Water-marked Direct Sequence Spread Spectrum (DSSS) or WDSSS technique, which embeds authentication information into pseudonoise (PN) sequences of a DSSS system. The design and implementation of the WDSSS prototype system on the GNU Radio/USRP SDR platform is discussed, as well as two watermark embedding methods, the maximized minimum distance method and the sub-sequence method. Theoretical analysis and experimental results on the WDSSS prototype system are presented to evaluate the performances of both the content signal and the watermark signal. Results show that, for the 11-chip PN sequence, increasing articial chip errors has aquantitatively predictable impact on the content signal, requiring 2 dB higher signal-to-noise ratio (SNR) to maintain an acceptable packet error rate (PER) for one additional ipped chip. In terms of the watermark signal, the two embedding methods demonstrated individual advantages in either PER or throughput. The maximized minimum distance method outperforms the sub-sequence embedding method with a 3 dB lower SNR requirement, while the latter provides 400 more throughput than the former with adequate SN

Hardware and Software Codesign of a JPEG2000 Watermarking Encoder

Analog technology has been around for a long time. The use of analog technology is necessary since we live in an analog world. However, the transmission and storage of analog technology is more complicated and in many cases less efficient than digital technology. Digital technology, on the other hand, provides fast means to be transmitted and stored. Digital technology continues to grow and it is more widely used than ever before. However, with the advent of new technology that can reproduce digital documents or images with unprecedented accuracy, it poses a risk to the intellectual rights of many artists and also on personal security. One way to protect intellectual rights of digital works is by embedding watermarks in them. The watermarks can be visible or invisible depending on the application and the final objective of the intellectual work. This thesis deals with watermarking images in the discrete wavelet transform domain. The watermarking process was done using the JPEG2000 compression standard as a platform. The hardware implementation was achieved using the ALTERA DSP Builder and SIMULINK software to program the DE2 ALTERA FPGA board. The JPEG2000 color transform and the wavelet transformation blocks were implemented using the hardware-in-the-loop (HIL) configuration

2005 Annual Research Symposium Abstract Book

2005 annual volume of abstracts for science research projects conducted by students at Trinity College