Self-Partial and Dynamic Reconfiguration Implementation for AES using FPGA

This paper addresses efficient hardware/software implementation approaches for the AES (Advanced Encryption Standard) algorithm and describes the design and performance testing algorithm for embedded system. Also, with the spread of reconfigurable hardware such as FPGAs (Field Programmable Gate Array) embedded cryptographic hardware became cost-effective. Nevertheless, it is worthy to note that nowadays, even hardwired cryptographic algorithms are not so safe. From another side, the self-reconfiguring platform is reported that enables an FPGA to dynamically reconfigure itself under the control of an embedded microprocessor. Hardware acceleration significantly increases the performance of embedded systems built on programmable logic. Allowing a FPGA-based MicroBlaze processor to self-select the coprocessors uses can help reduce area requirements and increase a system's versatility. The architecture proposed in this paper is an optimal hardware implementation algorithm and takes dynamic partially reconfigurable of FPGA. This implementation is good solution to preserve confidentiality and accessibility to the information in the numeric communication

Kecerdasan matematik-logik dalam kalangan pelajar sarjana Pendidikan Teknik dan Vokasional UTHM

Kecerdasan matematik-logik sering dikaitkan dengan penguasaan pelajar dalam subjek matematik. Pencapaian pelajar, khususnya pelajar Sarjana Pendidikan Teknik dan Vokasional, Universiti Tun Hussein Onn Malaysia (UTHM) dalam kursus Statistik dalam Penyelidikan sedikit sebanyak mempengaruhi pencapaian akademik pelajar. Oleh itu, kajian ini dijalankan untuk mengkaji pengaruh kecerdasan matematik-logik terhadap pencapaian pelajar dalam kursus Statistik dalam Penyelidikan. Kajian berbentuk tinjauan secara kuantitatif untuk melihat hubungan diantara dua pembolehubah iaitu pembolehubah tidak bersandar (kecerdasan matematik-logik) dan pembolehubah bersandar (penguasaan pelajar dalam kursus Statistik dalam Penyelidikan). Persampelan rawak mudah digunakan dalam kajian ini dengan mengambil sampel seramai 108 orang pelajar Sarjana Pendidikan Teknik dan Vokasional sebagai responden kajian. Data diperoleh daripada sampel dengan menggunakan borang soal selidik yang diolah berdasarkan alat pengukuran kecerdasan MIDAS (Multiple Intelligence Development Assessment Scales). Data dianalisis menggunakan perisian SPSS (Statistical Package for Social Science) versi 16.0 yang melibatkan ujian statistik skor min dan kolerasi pangkat Spearman. Hasil dapatan kajian menunjukkan tahap kecenderungan kecerdasan matematik-logik pelajar berada pada tahap yang tinggi dan mempunyai hubungan yang signifikan dengan pencapaian pelajar dalam kursus Statistik dalam Penyelidikan. Berdasarkan dapatan kajian boleh disimpulkan bahawa kecerdasan matematik-logik dapat dijadikan kayu ukur dalam memastikan kejayaan pelajar

A new countermeasure against side-channel attacks based on hardware-software co-design

This paper aims at presenting a new countermeasure against Side-Channel Analysis (SCA) attacks, whose implementation is based on a hardware-software co-design. The hardware architecture consists of a microprocessor, which executes the algorithm using a false key, and a coprocessor that performs several operations that are necessary to retrieve the original text that was encrypted with the real key. The coprocessor hardly affects the power consumption of the device, so that any classical attack based on such power consumption would reveal a false key. Additionally, as the operations carried out by the coprocessor are performed in parallel with the microprocessor, the execution time devoted for encrypting a specific text is not affected by the proposed countermeasure. In order to verify the correctness of our proposal, the system was implemented on a Virtex 5 FPGA. Different SCA attacks were performed on several functions of AES algorithm. Experimental results show in all cases that the system is effectively protected by revealing a false encryption key.Peer ReviewedPreprin

Hardware architecture implemented on FPGA for protecting cryptographic keys against side-channel attacks

This paper presents a new hardware architecture designed for protecting the key of cryptographic algorithms against attacks by side-channel analysis (SCA). Unlike previous approaches already published, the fortress of the proposed architecture is based on revealing a false key. Such a false key is obtained when the leakage information, related to either the power consumption or the electromagnetic radiation (EM) emitted by the hardware device, is analysed by means of a classical statistical method. In fact, the trace of power consumption (or the EM) does not reveal any significant sign of protection in its behaviour or shape. Experimental results were obtained by using a Virtex 5 FPGA, on which a 128-bit version of the standard AES encryption algorithm was implemented. The architecture could easily be extrapolated to an ASIC device based on standard cell libraries. The system is capable of concealing the real key when various attacks are performed on the AES algorithm, using two statistical methods which are based on correlation, the Welch’s t-test and the difference of means.Peer ReviewedPostprint (author's final draft

VLSI implementation of AES algorithm

In the present era of information processing through computers and access of private information over the internet like bank account information even the transaction of money, business deal through video conferencing, encryption of the messages in various forms has become inevitable. There are mainly two types of encryption algorithms, private key (also called symmetric key having single key for encryption and decryption) and public key (separate key for encryption and decryption). In the present work, hardware optimization for AES architecture has been done in different stages. The hardware comparison results show that as AES architecture has critical path delay of 9.78 ns when conventional s-box is used, whereas it has critical path delay of 8.17 ns using proposed s-box architecture. The total clock cycles required to encrypt 128 bits of data using proposed AES architecture are 86 and therefore, throughput of the AES design in Spartan-6 of Xilinx FPGA is approximately 182.2 Mbits/s. To achieve the very high speed, full custom design of s-box in composite field has been done for the proposed s-box architecture in Cadence Virtuoso. The novel XOR gate is proposed for use in s-box design which is efficient in terms of delay and power along with high noise margin. The implementation has been done in 180 nm UMC technology. Total dynamic power in the proposed XOR gate is 0.63 µW as compared to 5.27 µW in the existing design of XOR. The designed s-box using proposed XOR occupies a total area of 27348 µm2. The s-box chip consumes 22.6 µW dynamic power and has 8.2 ns delay after post layout simulation has been performed