On the testability of SDL specifications

The problem of testing from an SDL specification is often complicated by the presence of infeasible paths. This paper introduces an approach for transforming a class of SDL specification in order to eliminate or reduce the infeasible path problem. This approach is divided into two phases in order to aid generality. First the SDL specification is rewritten to create a normal form extended finite state machine (NF-EFSM). This NF-EFSM is then expanded in order to produce a state machine in which the test criterion may be satisfied using paths that are known to be feasible. The expansion process is guaranteed to terminate. Where the expansion process may lead to an excessively large state machine, this process may be terminated early and feasible paths added. The approach is illustrated through being applied to the Initiator process of the Inres protocol

Estelle-based test generation tool

A test design tool for functional analysis and test derivation of protocols formally specified using an extended finitestate machine model is presented. The formal description language supported is Estelle. The tool's main components include a compiler, a normalizer, a multiple module transition tour generator and several interactive programs. The tool is based on a static analysis of Estelle called normalization, which is explained in detail with various examples. The normalized specification facilitates graphical displays of the control and data flow in the specification by the interactive tools. Next discussed is test generation, which is based on verifying the control and data flow. First the data flow graph must be decomposed into blocks where each block represents the data flow in a protocol function. From the control graph the tool generates transition tours, and then test sequences are derived from the transition tour to test each function. The performance of the tool on various applications is also included. © 1991

SAVCBS 2005 Proceedings: Specification and Verification of Component-Based Systems

This workshop is concerned with how formal (i.e., mathematical) techniques can be or should be used to establish a suitable foundation for the specification and verification of component-based systems. Component-based systems are a growing concern for the software engineering community. Specification and reasoning techniques are urgently needed to permit composition of systems from components. Component-based specification and verification is also vital for scaling advanced verification techniques such as extended static analysis and model checking to the size of real systems. The workshop will consider formalization of both functional and non-functional behavior, such as performance or reliability. This workshop brings together researchers and practitioners in the areas of component-based software and formal methods to address the open problems in modular specification and verification of systems composed from components. We are interested in bridging the gap between principles and practice. The intent of bringing participants together at the workshop is to help form a community-oriented understanding of the relevant research problems and help steer formal methods research in a direction that will address the problems of component-based systems. For example, researchers in formal methods have only recently begun to study principles of object-oriented software specification and verification, but do not yet have a good handle on how inheritance can be exploited in specification and verification. Other issues are also important in the practice of component-based systems, such as concurrency, mechanization and scalability, performance (time and space), reusability, and understandability. The aim is to brainstorm about these and related topics to understand both the problems involved and how formal techniques may be useful in solving them

Tailored Protocol Development Using ESTEREL

The rapid evolution of networking and the multiplication of new applications re-emphasizes the importance of the efficient communication supports. Implementations must be able to take maximal advantage of the details of application-specific semantics and of specific networking environments. In other words, the application needs to have more control over data transmission. Such control can be obtained by tailoring the communication facilities (or protocols) to the application characteritics, and by integrating the communication control to the application. Because such a task is too complex to be realized manually, we propose to automate the protocol development process using a formal approach. This report presents our approach to the automated design and implementation of application- specific communication protocols based on information provided by the application. Starting from the formal description of an application, our approach is based on a tool called "Protocol Compiler" that will automatically produce the implementation of a communication protocol tailored to the application. The formalism we use is ESTEREL, a synchronous reactive language dedicated to the description of real-time systems. Protocol description and verification using ESTEREL are described, as well as protocol optimization and implementation principles

Using formal methods to support testing

Formal methods and testing are two important approaches that assist in the development of high quality software. While traditionally these approaches have been seen as rivals, in recent years a new consensus has developed in which they are seen as complementary. This article reviews the state of the art regarding ways in which the presence of a formal specification can be used to assist testing

Easing the Transition from Inspiration to Implementation: A Rapid Prototyping Platform for Wireless Medium Access Control Protocols

Packet broadcast networks are in widespread use in modern wireless communication systems. Medium access control is a key functionality within such technologies. A substantial research effort has been and continues to be invested into the study of existing protocols and the development of new and specialised ones. Academic researchers are restricted in their studies by an absence of suitable wireless MAC protocol development methods. This thesis describes an environment which allows rapid prototyping and evaluation of wireless medium access control protocols. The proposed design flow allows specification of the protocol using the specification and description language (SDL) formal description technique. A tool is presented to convert the SDL protocol description into a C++ model suitable for integration into both simulation and implementation environments. Simulations at various levels of abstraction are shown to be relevant at different stages of protocol design. Environments based on the Cinderella SDL simulator and the ns-2 network simulator have been developed which allow early functional verification, along with detailed and accurate performance analysis of protocols under development. A hardware platform is presented which allows implementation of protocols with flexibility in the hardware/software trade-off. Measurement facilities are integral to the hardware framework, and provide a means for accurate real-world feedback on protocol performance

Hardware/Software Codesign

The current state of the art technology in integrated circuits allows the incorporation of multiple processor cores and memory arrays, in addition to application specific hardware, on a single substrate. As silicon technology has become more advanced, allowing the implementation of more complex designs, systems have begun to incorporate considerable amounts of embedded software [3]. Thus it becomes increasingly necessary for the system designers to have knowledge on both hardware and software to make efficient design tradeoffs. This is where hardware/software codesign comes into existence