An enhanced static-list scheduling algorithm for temporal partitioning onto RPUs

This paper presents a novel algorithm for temporal partitioning of graphs representing a behavioral description. The algorithm is based on an extension of the traditional static-list scheduling that tailors it to resolve both scheduling and temporal partitioning. The nodes to be mapped into a partition are selected based on a statically computed cost model. The cost for each node integrates communication effects, the critical path length, and the possibility of the critical path to hide the delay of parallel nodes. In order to alleviate the runtime there is no dynamic update of the costs. A comparison of the algorithm to other schedulers and with close-to-optimum results obtained with a simulated annealing approach is shown. The presented algorithm has been implemented and the results show that it is robust, effective, and efficient, and when compared to other methods finds very good results in small amounts of CPU time

On-line defragmentation for run-time partially reconfigurable FPGAs

Dynamically reconfigurable systems have benefited from a new class of FPGAs recently introduced into the market, which allow partial and dynamic reconfiguration at run time, enabling multiple independent processes from different applications to share the same device, swapping them as needed. When the sequence of tasks to be performed is not predictable, resource allocation decisions have to be made online, producing fragmentation of the FPGA logic space. A rearrangement may be necessary to get enough contiguous space to efficiently implement new incoming processes, avoiding the spreading of their components and, as a result, the degradation of their performance. This paper presents a novel active replication mechanism for configurable logic blocks (CLBs), able to implement online rearrangements, defragmenting the available FPGA resources without disturbing currently running processes

Proceedings of the 9th MIT/ONR workshop on C3 Systems, held at Naval Postgraduate School and Hilton Inn Resort Hotel, Monterey, California June 2 through June 5, 1986

GRSN 627729"December 1986."Includes bibliographical references and index.Sponsored by Massachusetts Institute of Technology, Laboratory for Information and Decision Systems, Cambridge, Mass., with support from the Office of Naval Research. ONR/N00014-77-C-0532(NR041-519) Sponsored in cooperation with IEEE Control Systems Society, Technical Committee on C.edited by Michael Athans, Alexander H. Levis