DESIGN AND IMPLEMENTATION OF AN EFFICIENT IMAGE COMPRESSOR FOR WIRELESS CAPSULE ENDOSCOPY

Capsule endoscope (CE) is a diagnosis tool for gastrointestinal (GI) diseases. Area and power are the two important parameters for the components used in CE. To optimize these two parameters, an efficient image compressor is desired. The mage compressor should be able to sufficiently compress the captured images to save transmission power, retain reconstruction quality for accurate diagnosis and consumes small physical area. To meet all of the above mentioned conditions, we have studied several transform coding based lossy compression algorithms in this thesis. The core computation tool of these compressors is the Discrete Cosine Transform (DCT) kernel. The DCT accumulates the distributed energy of an image in a small centralized area and supports more compression with non-significant quality degradation. The conventional DCT requires complex floating point multiplication, which is not feasible for wireless capsule endoscopy (WCE) application because of its high implementation cost. So, an integer version of the DCT, known as iDCT, is used in this work. Several low complexity iDCTs along with different color space converters (such as, YUV, YEF, YCgCo) were combined to obtain the desired compression level. At the end a quantization stage is used in the proposed algorithm to achieve further compression. We have analyzed the endoscopic images and based on their properties, three quantization matrix sets have been proposed for three color planes. The algorithms are verified at both software (using MATLAB) and hardware (using HDL Verilog coding) levels. In the end, the performance of all the proposed schemes has been evaluated for optimal operation in WCE application

A low complexity image compression algorithm for Bayer color filter array

Digital image in their raw form requires an excessive amount of storage capacity. Image compression is a process of reducing the cost of storage and transmission of image data. The compression algorithm reduces the file size so that it requires less storage or transmission bandwidth. This work presents a new color transformation and compression algorithm for the Bayer color filter array (CFA) images. In a full color image, each pixel contains R, G, and B components. A CFA image contains single channel information in each pixel position, demosaicking is required to construct a full color image. For each pixel, demosaicking constructs the missing two-color information by using information from neighbouring pixels. After demosaicking, each pixel contains R, G, and B information, and a full color image is constructed. Conventional CFA compression occurs after the demosaicking. However, the Bayer CFA image can be compressed before demosaicking which is called compression-first method, and the algorithm proposed in this research follows the compression-first or direct compression method. The compression-first method applies the compression algorithm directly onto the CFA data and shifts demosaicking to the other end of the transmission and storage process. The advantage of the compression-first method is that it requires three time less transmission bandwidth for each pixel than conventional compression. Compression-first method of CFA data produces spatial redundancy, artifacts, and false high frequencies. The process requires a color transformation with less correlation among the color components than that Bayer RGB color space. This work analyzes correlation coefficient, standard deviation, entropy, and intensity range of the Bayer RGB color components. The analysis provides two efficient color transformations in terms of features of color transformation. The proposed color components show lesser correlation coefficient than occurs with the Bayer RGB color components. Color transformations reduce both the spatial and spectral redundancies of the Bayer CFA image. After color transformation, the components are independently encoded using differential pulse-code modulation (DPCM) in raster order fashion. The residue error of DPCM is mapped to a positive integer for the adaptive Golomb rice code. The compression algorithm includes both the adaptive Golomb rice and Unary coding to generate bit stream. Extensive simulation analysis is performed on both simulated CFA and real CFA datasets. This analysis is extended for the WCE (wireless capsule endoscopic) images. The compression algorithm is also realized with a simulated WCE CFA dataset. The results show that the proposed algorithm requires less bits per pixel than the conventional CFA compression. The algorithm also outperforms recent works on CFA compression algorithms for both real and simulated CFA datasets

Performance Improvement for Reconfigurable Processor System Design in IoT Health Care Monitoring Applications

This research focuses on critical hardware components of an Internet of Things (IoT) system for reconfigurable processing systems. Single-Instruction Multiple-Data (SIMD) processors have recently been utilized to preprocess data at energy-constrained sensor nodes or IoT gateways, saving significant energy and bandwidth for transmission. Using traditional CPU-based systems to implement machine learning algorithms is inefficient in terms of energy consumption. In the proposed method Single-Instruction Multiple-Data (SIMD) processors are assembled by scaling the largest possible operand value subunits into direct access to the internal memory, where the carry output of each unit is conditionally fed into the next unit based on the implementation of the SIMD Processor design for Internet of Things applications. Each method has evaluated sub-operations that contribute considerably to the overall potential of the design. If the single register file can complete the intended action, a zero (one)-signal is applied to each unit\u27s carry input. Multiplexers combine two or more adders, sending the carry signal from one unit into another if additional units are necessary to compute the sum. The outcome results compare high-speed end device techniques in terms of area and power consumption. The proposed SIMD processor-based IoT healthcare monitoring system with a MIMD processor\u27s performance analysis of comparison clearly demonstrates that the system produces decent outcomes. The suggested system has an area overhead of 85 m2, a power usage of 4.10 W, and a time delay of 20 ns

VLSI Design

This book provides some recent advances in design nanometer VLSI chips. The selected topics try to present some open problems and challenges with important topics ranging from design tools, new post-silicon devices, GPU-based parallel computing, emerging 3D integration, and antenna design. The book consists of two parts, with chapters such as: VLSI design for multi-sensor smart systems on a chip, Three-dimensional integrated circuits design for thousand-core processors, Parallel symbolic analysis of large analog circuits on GPU platforms, Algorithms for CAD tools VLSI design, A multilevel memetic algorithm for large SAT-encoded problems, etc

VLSI Implementation of a Cost-Efficient Loeffler-DCT Algorithm with Recursive CORDIC for DCT-Based Encoder

This paper presents a low-cost and high-quality; hardware-oriented; two-dimensional discrete cosine transform (2-D DCT) signal analyzer for image and video encoders. In order to reduce memory requirement and improve image quality; a novel Loeffler DCT based on a coordinate rotation digital computer (CORDIC) technique is proposed. In addition; the proposed algorithm is realized by a recursive CORDIC architecture instead of an unfolded CORDIC architecture with approximated scale factors. In the proposed design; a fully pipelined architecture is developed to efficiently increase operating frequency and throughput; and scale factors are implemented by using four hardware-sharing machines for complexity reduction. Thus; the computational complexity can be decreased significantly with only 0.01 dB loss deviated from the optimal image quality of the Loeffler DCT. Experimental results show that the proposed 2-D DCT spectral analyzer not only achieved a superior average peak signal–noise ratio (PSNR) compared to the previous CORDIC-DCT algorithms but also designed cost-efficient architecture for very large scale integration (VLSI) implementation. The proposed design was realized using a UMC 0.18-μm CMOS process with a synthesized gate count of 8.04 k and core area of 75,100 μm2. Its operating frequency was 100 MHz and power consumption was 4.17 mW. Moreover; this work had at least a 64.1% gate count reduction and saved at least 22.5% in power consumption compared to previous designs

Hybrid DWT-DCT algorithm for image and video compression applications

Digital image and video in their raw form require an enormous amount of storage capacity. Considering the important role played by digital imaging and video, it is necessary to develop a system that produces high degree of compression while preserving critical image/video information. There are various transformation techniques used for data compression. Discrete Cosine Transform (DCT) and Discrete Wavelet Transform (DWT) are the most commonly used transformation. DCT has high energy compaction property and requires less computational resources. On the other hand, DWT is multiresolution transformation. In this work, we propose a hybrid DWT-DCT algorithm for image compression and reconstruction taking benefit from the advantages of both algorithms. The algorithm performs the Discrete Cosine Transform (DCT) on the Discrete Wavelet Transform (DWT) coefficients. Simulations have been conducted on several natural, benchmark, medical and endoscopic images. Several QCIF, high definition, and endoscopic videos have also been used to demonstrate the advantage of the proposed scheme. The simulation results show that the proposed hybrid DWT-DCT algorithm performs much better than the standalone JPEG-based DCT, DWT, and WHT algorithms in terms of peak signal to noise ratio (PSNR), as well as visual perception at higher compression ratio. The new scheme reduces “false contouring” and “blocking artifacts” significantly. The rate distortion analysis shows that for a fixed level of distortion, the number of bits required to transmit the hybrid coefficients would be less than those required for other schemes Furthermore, the proposed algorithm is also compared with the some existing hybrid algorithms. The comparison results show that, the proposed hybrid algorithm has better performance and reconstruction quality. The proposed scheme is intended to be used as the image/video compressor engine in imaging and video applications