Atomistic Simulations of Flash Memory Materials Based on Chalcogenide Glasses

In this chapter, by using ab-initio molecular dynamics, we introduce the latest simulation results on two materials for flash memory devices: Ge2Sb2Te5 and Ge-Se-Cu-Ag. This chapter is a review of our previous work including some of our published figures and text in Cai et al. (2010) and Prasai & Drabold (2011) and also includes several new results.Comment: 24 pages, 20 figures. This is a chapter submitted for the book under the working title "Flash Memory" (to be published by Intech ISBN 978-953-307-272-2

Multi-port Memory Design for Advanced Computer Architectures

In this thesis, we describe and evaluate novel memory designs for multi-port on-chip and off-chip use in advanced computer architectures. We focus on combining multi-porting and evaluating the performance over a range of design parameters. Multi-porting is essential for caches and shared-data systems, especially multi-core System-on-chips (SOC). It can significantly increase the memory access throughput. We evaluate FinFET voltage-mode multi-port SRAM cells using different metrics including leakage current, static noise margin and read/write performance. Simulation results show that single-ended multi-port FinFET SRAMs with isolated read ports offer improved read stability and flexibility over classical double-ended structures at the expense of write performance. By increasing the size of the access transistors, we show that the single-ended multi-port structures can achieve equivalent write performance to the classical double-ended multi-port structure for 9% area overhead. Moreover, compared with CMOS SRAM, FinFET SRAM has better stability and standby power. We also describe new methods for the design of FinFET current-mode multi-port SRAM cells. Current-mode SRAMs avoid the full-swing of the bitline, reducing dynamic power and access time. However, that comes at the cost of voltage drop, which compromises stability. The design proposed in this thesis utilizes the feature of Independent Gate (IG) mode FinFET, which can leverage threshold voltage by controlling the back gate voltage, to merge two transistors into one through high-Vt and low-Vt transistors. This design not only reduces the voltage drop, but it also reduces the area in multi-port current-mode SRAM design. For off-chip memory, we propose a novel two-port 1-read, 1-write (1R1W) phasechange memory (PCM) cell, which significantly reduces the probability of blocking at the bank levels. Different from the traditional PCM cell, the access transistors are at the top and connected to the bitline. We use Verilog-A to model the behavior of Ge2Sb2Te5 (GST: the storage component). We evaluate the performance of the two-port cell by transistor sizing and voltage pumping. Simulation results show that pMOS transistor is more practical than nMOS transistor as the access device when both area and power are considered. The estimated area overhead is 1.7�, compared to single-port PCM cell. In brief, the contribution we make in this thesis is that we propose and evaluate three different kinds of multi-port memories that are favorable for advanced computer architectures

Reconfigurable three-terminal logic devices using phase-change materials

Conventional solid-state and mass storage memories (such as SRAM, DRAM and the hard disk drive HDD) are facing many technological challenges to meet the ever-increasing demand for fast, low power and cheap data storage solutions. This is compounded by the current conventional computer architectures (such as the von Neumann architecture) with separate processing and storage functionalities and hence data transfer bottlenecks and increased silicon footprint. Beyond the von Neumann computer architecture, the combination of arithmetic-logic processing and (collocally) storage circuits provide a new and promising alternative for computer systems that overcome the many limitations of current technology. However, there are many technical challenges that face the implementation of universal blocks of both logic and memory functions using conventional silicon technology (transistor-transistor logic - TTL, and complementary metal oxide semiconductors - CMOS). Phase-change materials, such as Ge2Sb2Te5 (GST), provide a potential complement or replacement to these technologies to provide both processing and, collocally, storage capability. Existing research in phase-change memory technologies focused on two-terminal non-volatile devices for different memory and logic applications due to their ability to achieve logic-resistive switching in nanosecond time scale, their scalability down to few nanometer-scale cells, and low power requirements. To perform logic functionality, current two-terminal phase-change logic devices need to be connected in series or parallel circuits, and require sequential inputs to perform the required logic function (such as NAND and NOR). In this research programme, three-terminal (3T) non-volatile phase-change memories are proposed and investigated as potential alternative logic cells with simultaneous inputs as reconfigurable, non-volatile logic devices. A vertical 3T logic device structure is proposed in this work based on existing phase-change based memory cell architecture and original concept work by Ovshinsky. A comprehensive, multi-physics finite-element model of the vertical 3T device was constructed in Comsol Multiphysics. This model solves Laplace's equation for the electric potential due to the application of voltage sources. The calculated electric potential and fields provide the Joule heating source in the device, which is used to compute the temperature distribution through solution of the heat diffusion equation, which is necessary to activate the thermally-driven phase transition process. The physically realistic and computationally efficient nucleation- growth model was numerically implemented to model the phase change and resistance change in the Ge2Sb2Te5 (GST) phase-change material in the device, which is combined with the finite- element model using the Matlab programming interface. The changes in electrical and thermal conductivities in the GST region are taken into account following the thermally activated phase transformations between the amorphous-crystalline states using effective medium theory. To determine the appropriate voltage and temperature conditions for the SET and RESET operations, and to optimise the materials and thicknesses of the thermal and heating layers in the device, comprehensive steady-state parametric simulations were carried out using the finite-element multi-physics model. Simulations of transient cycles of writing (SET) and erasing (RESET) processes using appropriate voltage pulses were then carried out on the designed vertical 3T device to study the phase transformations for practical reconfigurable logic operations. The simulations indicated excellent resistance contrast between the logic 1 and 0 states, and successfully demonstrated the feasibility of programming the logic functions of NAND and NOR gates using this 3T configuration

Analysis of Photoconductive Properties in Ge\u3csub\u3e2\u3c/sub\u3eSb\u3csub\u3e2\u3c/sub\u3eTe\u3csub\u3e5\u3c/sub\u3e (GST) Chalcogenide Films for Applications in Novel Electronics

This thesis investigated the thermal phase-change properties in Ge2Sb2Te5 (GST) chalcogenide-based films and determined the feasibility of coupling the GST with photosensitive DNA material for novel optical device applications. Modeling and testing of GST were researched with the approach that GST would react as a resistive mechanism through thermal manipulation. A test structure was fabricated with a 2-micronmeter MEMS fabrication process. GST material was deposited (by RF sputtering) on the surface of the test structures. The GST was analyzed primarily in the amorphous to crystalline transition states due to more distinct changes in the resistance between partial states. Using both filtered light (via a monochromator), and non-filtered white light, light was incident on the GST for photo response testing. A biased voltage was applied to the device and the current change was measured. The GST was tested electrically, applying a current sweep across the device and measuring change in resistance as the GST changed states. Data recorded on the thermal properties of GST leading to resistive changes from both optical and electrical sources was analyzed. The results of this research indicate how future optical and electrical testing of the GST can be improved. The data measured by testing the GST electrically was compared to other research data (following similar testing procedures), revealing that optimal designs need sub-micro layers of GST with electrodes places above and below the GST. It was concluded that higher power light sources will be needed to continue exploring the optical reaction of GST in future research

Electronic, optical and thermal properties of the hexagonal and fcc Ge2Sb2Te5 chalcogenide from first-principle calculations

We present a comprehensive computational study on the properties of face-centered cubic and hexagonal chalcogenide Ge2Sb2Te5. We calculate the electronic structure using density functional theory (DFT); the obtained density of states (DOS) compares favorably with experiments, also looking suitable for transport analysis. Optical constants including refraction index and absorption coefficient capture major experimental features, aside from an energy shift owed to an underestimate of the band gap that is typical of DFT calculations. We also compute the phonon DOS for the hexagonal phase, obtaining a speed of sound and thermal conductivity in good agreement with the experimental lattice contribution. The calculated heat capacity reaches ~ 1.4 x 106 J/(m3 K) at high temperature, in agreement with experimental data, and provides insight into the low-temperature range (< 150 K), where data are unavailable.Comment: 19 pages, 8 figure

Study on the Novel PRAM cell structure for reducing reset current

본 논문에서는 차세대 메모리인 상변화 메모리(Phase change random access memory)의 지우기 전류 감소를 위한 새로운 셀 구조에 관해 고찰하였다. 기록, 소거, 재생 속도, 재기록, 횟수 등을 포함한 성능에서 DRAM 급의 성능 특성을 가지며 소자구조 및 제작공정이 단순하여 정보저장 및 처리 용량대비 저가격화 달성이 용이한 상변화 메모리(PRAM)가 차세대 비휘발성 메모리로 주목 받고 있다. 그러나 상변화 메모리의 지우기 동작전류는 타 메모리 소자에 비해 큰 값을 나타내는 단점이 있어 상변화 메모리가 기존의 메모리 소자를 대체하기위한 경쟁력을 갖추기 위해서는 지우기 동작 전류를 낮추어야 한다. 상변화 메모리의 지우기 동작 전류를 낮추기 위해 상변화 물질, 발열전극 물질 및 셀 구조 변화 등의 연구가 진행 중이다. 그 중에서 셀 구조를 변형함으로써 지우기 전류를 줄여보고자 하는 연구가 이루어지고 있다. 본 연구는 PRAM의 지우기 전류를 줄이기 위해 상변화 물질 자체를 발열체로 사용하는 Pore형 PRAM 소자를 제작하여 소자 특성을 조사하였다. 또한 3차원 유한 요소 해석 프로그램을 이용하여 나노 스케일 PRAM의 GST박막의 두께에 따른 PRAM의 지우기 전류와 온도에 관해 조사하였고, 상변화 물질의 두께가 얇아질수록 지우기 전류가 증가하는 것을 알게 되었다. 지우기 전류의 증가를 막기 위해 SiO₂ 열 방지층을 사용하는 새로운 구조의 PRAM cell을 제안하였고 또한 지우기 전류와 온도에 관한 조사를 하였다. 200 ㎚ 의 두께의 GST박막의 두께에서 기존의 구조와 새로운 구조의 PRAM을 비교하였을 때, 새로운 구조의 PRAM cell에서 온도는 536.60 ℃ 에서 817 ℃ 로 크게 증가하였고, 지우기 전류는 17.4 ㎃ to 13.7 ㎃ 로 감소하였음을 알 수 있었다. 이 결과는 새로운 구조의 PRAM cell이 열 방지층으로서 효과적으로 작용해 지우기 전류를 감소시킴을 알 수 있었다.Today, the market for non-volatile memory is dominated by the Flash technology. Due to the increasing cost of down scaling Flash technology, the memory industry is searching for alternative memory concept. One of most promising candidates is the electrical phase change technology PRAM. In this paper, we fabricated the PRAM unit cell and investigated electro and thermal characteristics of PRAM unit cell with novel structure using SiO₂ heat blocking layer. As thickness of GST thin film decreased from 400 ㎚ to 300 ㎚, reset current and temperature changed a bit but did not affect so much memory cell operation. But as thickness of GST thin decreased from 300 ㎚ to 200 ㎚, reset current increased from 15 ㎃ to 17.4 ㎃ and temperature decreased from 704.86 ℃ to 536.60 ℃. As reset current and temperature changed like at 200 ㎚ thickness of GST thin film, the memory cell operation did not work as normal. From this results, we investigated material parameters of heater electrode for why reset current and temperature changed. After investigation, we found that heat which was generated between phase change material GST and heater electrode TiN was given to top electrode W due to thin thickness of GST thin film. We have throughly investigated the decreasing of temperature of 200 ㎚ thickness of GST thin film and found that the severe heat loss occurred at top electrode. In the case of 200 ㎚ thickness of GST thin film, a heat rapidly transferred to top electrode before melting temperature. A heat which contacted with top electrode transferred easily to outside and temperature decreased. Therefore, novel structure PRAM which deposited SiO₂ blocking layer instead of part of top electrode was proposed. The SiO₂ blocking layer which is dielectric layer can protect the heat to give off through top electrode. In comparison with conventional PRAM at 200 ㎚ GST thin film thickness, temperature of novel structure PRAM highly increased from 536.60 ℃ to 817 ℃ and reset current of novel structure PRAM decreased abruptly. from 17.4 ㎃ to 13.7 ㎃. This result shows that novel SiO₂ blocking layer of PRAM successfully protected heat to give off to top electrode.Chapter 1. Introduction = 1 Chapter 2. What is the PRAM = 4 2.1 Definition and background of the PRAM = 4 2.2 Theory of operation = 7 2.3 Method of reduction of reset current = 11 2.4 Electromagnetic analysis = 12 2.5 Thermal analysis = 14 Chapter 3. Experimental = 17 3.1 Fabrication procedure = 17 3.2 Finite element analysis = 21 Chapter 4. Results and discussion = 24 4.1 Electro-thermal characteristics of the PRAM = 24 4.1.1 Electrical property = 24 4.1.2 Electro-thermal analysis = 27 4.1.3 Effect of thickness of Ge2Sb2Te5 = 29 4.2 Effect of novel structure PRAM unit cell with heat blocking layer = 33 4.2.1 Finite element analysis model = 33 4.2.2 Electro-thermal analysis = 34 4.3 Effect of heat blocking layer in planar type PRAM = 38 4.3.1 Electro-thermal analysis = 38 4.3.2 Effect of heat blocking layer = 41 Chapter 5. Conclusion = 45 Chapter 6. Reference = 4

A Model for Multilevel Phase-Change Memories Incorporating Resistance Drift Effects

Phase change memories are emerging as a most promising technology for future nonvolatile, solid-state, electrical storage. However, to compete effectively in mainstream storage applications, a multilevel cell capability is most desirable. Unfortunately, phase-change memories exhibit a temporal drift in programmed resistance (and in threshold switching voltage) which appears to be a fundamental and universal property of the amorphous or partially amorphous phase. Phase-change device models should therefore include these drift effects in a realistic way so that circuit and systems designers can assess the likely performance of multilevel phase-change memories in a variety of potential applications. In this paper, therefore, we present a comprehensive SPICE-based model for phase-change devices that includes the capability for programming into multiple resistance levels, the prediction of the drift of cell resistance (and threshold voltage) with time, and the capability for modeling the randomness inherent to the resistance drift phenomenon. Simulations of multilevel programming and drift phenomena using the model are presented and compared to experimental results, with which there is very good agreement

Time-Domain Analysis of Chalcogenide Threshold Switching: From ns to ps Scale

A space- and time-dependent theoretical model based on a trap-assisted, charge-transport framework for the amorphous phase of a chalcogenide material is used here to interpret available experimental results for the electric current of nanoscale devices in the ns–ps time domain. A numerical solution of the constitutive equations of the model for a time-dependent bias has been carried out for GST-225 devices. The “intrinsic” rise time of the device current after the application of a suitable external bias is controlled by the microscopic relaxation of the mobile-carrier population to the steady-state value. Furthermore, the analysis is extended to include the effect of the external circuit on the electrical switching. A quantitative estimate of the current delay time due to unavoidable parasitic effects is made for the optimised electrical set up configurations recently used by experimental groups