An Efficient Methodology for Calibrating Traffic Flow Models Based on Bisection Analysis

As urban planning becomes more sophisticated, the accurate detection and counting of pedestrians and cyclists become more important. Accurate counts can be used to determine the need for additional pedestrian walkways and intersection reorganization, among other planning initiatives. In this project, a camera-based approach is implemented to create a real-time pedestrian and cyclist counting system which is regularly accurate to 85% and often achieves higher accuracy. The approach retasks a state-of-the-art traffic camera, the Autoscope Solo Terra, for pedestrian and bicyclist counting. Object detection regions are sized to identify multiple pedestrians moving in either direction on an urban sidewalk and bicyclists in an adjacent bicycle lane. Collected results are processed in real time, eliminating the need for video storage and postprocessing. In this paper, results are presented for a pedestrian walkway for pedestrian flow up to 108 persons/min and the limitations of the implemented system are enumerated. Both pedestrian and cyclist counting accuracy of over 90% is achieved

Modeling Interactions Between Human Factors and Traffic Flow Characteristics

To serve research needs for traffic flow model development and highway safety enhancement, we model interactions between human factors and traffic flow character- istics, this topic includes methods on collecting data, modeling impacts of parameters on flow, and calibrating parameters on observed data. An example of successful traf- fic data collection is NGSIM data, which contains location, speed, and acceleration information of vehicles. An algorithm was designed to match and extract vehicles’ trajectory records, and utilize the extracted information for pattern recognition of lane changing maneuvers. This algorithm reads records from an NGSIM data set, pick out vehicles executing lane changing maneuvers, and note the corresponding time stamps. Also through matching these records by vehicle ID and time stamp, we obtain a map of vehicles when a lane changing is happening, thus calculating gaps and relative speeds becomes possible. An example of utilizing these information is pattern recognition on lane changing maneuvers. We analyze lane changing maneu- vers with speed data and gap data. The approach with speed data shows convincing results, as most lane changing vehicles have a descending and then ascending pattern on their speed profiles before executing the maneuver. On the other hand we can use collected data for calibrating parameters in traffic flow models. A heuristic method- ology is implemented to provide results with high accuracy, high efficiency and high robustness. Techniques include data aggregation and bisection analysis are applied in this approach to ensure achieving these goals and further requirements. Two traf- fic flow simulation models, Longitudinal Control Model (LCM) and Newell’s Model are calibrated by applying this approach using traffic data collected at Georgia 400 highway in July, 2003, with satisfying accuracy and robustness produced in a running time of less than 2 seconds. Meanwhile we can enhance human factors by applying new technologies, and connected vehicle is a good example which is rapidly devel- oping. Future vehicles will be able to communicate with each other which greatly improves drivers’ situational awareness. Consequently, drivers may be able to re- spond earlier to safety hazards before they manifest themselves in forms of imminent danger. Therefore, the overall effect of this technology can be attributed to drivers’ enhanced perception-reaction (P-R) capability which, in turn, translates to improved flow and capacity. However, it is critical to quantify such benefits before large-scale investment is made. In our research, a statistical transformation model is formulated to predict the probability distribution function of flow. By entering distributions of P-R time and enhanced P-R time, this model helps compare before and after distri- butions of traffic flow, based on which benefits of connected vehicles on traffic flow can be analyzed

Driving the Network-on-Chip Revolution to Remove the Interconnect Bottleneck in Nanoscale Multi-Processor Systems-on-Chip

The sustained demand for faster, more powerful chips has been met by the availability of chip manufacturing processes allowing for the integration of increasing numbers of computation units onto a single die. The resulting outcome, especially in the embedded domain, has often been called SYSTEM-ON-CHIP (SoC) or MULTI-PROCESSOR SYSTEM-ON-CHIP (MP-SoC). MPSoC design brings to the foreground a large number of challenges, one of the most prominent of which is the design of the chip interconnection. With a number of on-chip blocks presently ranging in the tens, and quickly approaching the hundreds, the novel issue of how to best provide on-chip communication resources is clearly felt. NETWORKS-ON-CHIPS (NoCs) are the most comprehensive and scalable answer to this design concern. By bringing large-scale networking concepts to the on-chip domain, they guarantee a structured answer to present and future communication requirements. The point-to-point connection and packet switching paradigms they involve are also of great help in minimizing wiring overhead and physical routing issues. However, as with any technology of recent inception, NoC design is still an evolving discipline. Several main areas of interest require deep investigation for NoCs to become viable solutions: • The design of the NoC architecture needs to strike the best tradeoff among performance, features and the tight area and power constraints of the onchip domain. • Simulation and verification infrastructure must be put in place to explore, validate and optimize the NoC performance. • NoCs offer a huge design space, thanks to their extreme customizability in terms of topology and architectural parameters. Design tools are needed to prune this space and pick the best solutions. • Even more so given their global, distributed nature, it is essential to evaluate the physical implementation of NoCs to evaluate their suitability for next-generation designs and their area and power costs. This dissertation performs a design space exploration of network-on-chip architectures, in order to point-out the trade-offs associated with the design of each individual network building blocks and with the design of network topology overall. The design space exploration is preceded by a comparative analysis of state-of-the-art interconnect fabrics with themselves and with early networkon- chip prototypes. The ultimate objective is to point out the key advantages that NoC realizations provide with respect to state-of-the-art communication infrastructures and to point out the challenges that lie ahead in order to make this new interconnect technology come true. Among these latter, technologyrelated challenges are emerging that call for dedicated design techniques at all levels of the design hierarchy. In particular, leakage power dissipation, containment of process variations and of their effects. The achievement of the above objectives was enabled by means of a NoC simulation environment for cycleaccurate modelling and simulation and by means of a back-end facility for the study of NoC physical implementation effects. Overall, all the results provided by this work have been validated on actual silicon layout

Floorplan-Aware High Performance NoC Design

Las actuales arquitecturas de m�ltiples n�cleos como los chip multiprocesadores (CMP) y soluciones multiprocesador para sistemas dentro del chip (MPSoCs) han adoptado a las redes dentro del chip (NoC) como elemento -ptimo para la inter-conexi-n de los diversos elementos de dichos sistemas. En este sentido, fabricantes de CMPs y MPSoCs han adoptado NoCs sencillas, generalmente con una topolog'a en malla o anillo, ya que son suficientes para satisfacer las necesidades de los sistemas actuales. Sin embargo a medida que los requerimientos del sistema -- baja latencia y alto rendimiento -- se hacen m�s exigentes, estas redes tan simples dejan de ser una soluci-n real. As', la comunidad investigadora ha propuesto y analizado NoCs m�s complejas. No obstante, estas soluciones son m�s dif'ciles de implementar -- especialmente los enlaces largos -- haciendo que este tipo de topolog'as complejas sean demasiado costosas o incluso inviables. En esta tesis, presentamos una metodolog'a de dise-o que minimiza la p�rdida de prestaciones de la red debido a su implementaci-n real. Los principales problemas que se encuentran al implementar una NoC son los conmutadores y los enlaces largos. En esta tesis, el conmutador se ha hecho modular, es decir, formado como uni-n de m-dulos m�s peque-os. En nuestro caso, los m-dulos son id�nticos, donde cada m-dulo es capaz de arbitrar, conmutar, y almacenar los mensajes que le llegan. Posteriormente, flexibilizamos la colocaci-n de estos m-dulos en el chip, permitiendo que m-dulos de un mismo conmutador est�n distribuidos por el chip. Esta metodolog'a de dise-o la hemos aplicado a diferentes escenarios. Primeramente, hemos introducido nuestro conmutador modular en NoCs con topolog'as conocidas como la malla 2D. Los resultados muestran como la modularidad y la distribuci-n del conmutador reducen la latencia y el consumo de potencia de la red. En segundo lugar, hemos utilizado nuestra metodolog'a de dise-o para implementar un crossbar distribuidRoca Pérez, A. (2012). Floorplan-Aware High Performance NoC Design [Tesis doctoral no publicada]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/17844Palanci

City-Scale Traffic Simulation - Performance and Calibration

Ph.DDOCTOR OF PHILOSOPH

Dispatching and Rescheduling Tasks and Their Interactions with Travel Demand and the Energy Domain: Models and Algorithms

Abstract The paper aims to provide an overview of the key factors to consider when performing reliable modelling of rail services. Given our underlying belief that to build a robust simulation environment a rail service cannot be considered an isolated system, also the connected systems, which influence and, in turn, are influenced by such services, must be properly modelled. For this purpose, an extensive overview of the rail simulation and optimisation models proposed in the literature is first provided. Rail simulation models are classified according to the level of detail implemented (microscopic, mesoscopic and macroscopic), the variables involved (deterministic and stochastic) and the processing techniques adopted (synchronous and asynchronous). By contrast, within rail optimisation models, both planning (timetabling) and management (rescheduling) phases are discussed. The main issues concerning the interaction of rail services with travel demand flows and the energy domain are also described. Finally, in an attempt to provide a comprehensive framework an overview of the main metaheuristic resolution techniques used in the planning and management phases is shown

Planning methodology for alternative intersection design and selection

The recent publication of the 6th Edition of the Highway Capacity Manual included a chapter on Ramp Terminals and Alternative Intersections that introduces various alternative intersection designs and assesses the performance of Median U-turn, Restricted crossing U-turn and Displaced left-turn intersections. Missing from the literature is an alternative intersection selection tool for identifying whether an alternative intersection would be successful under local conditions. With limited information of organized alternative intersection research, most planners must rely heavily on their personal judgement while selecting the most suitable intersection designs. As appealing as alternative intersections are, there is no comprehensive methodology for planners to evaluate all possible designs and locate the best option. Several studies have been performed on identifying the selection of the most appropriate alternative intersection. As straightforward as they are, they failed to accommodate the Highway Capacity Manual (HCM) and are highly dependent on the professional judgment of the planners. This dissertation aims to design a selection methodology that is easy to use and HCM compatible and independent of personal judgments. The selection procedure is composed of three stages. The goal of the first stage is to clarify the objectives and concerns of planners in the selection of candidate intersections. This stage should identify the treatment objectives (for existing intersections) and stakeholders’ concerns (for new intersections). If more than one objective were identified, the planners should assign a weight for each objective. A questionnaire should be used in collecting this information. The second stage is to filter out some candidate designs before the detailed analysis. This stage tries to generalize the range of application for each Unconventional Alternative Intersection Design (UAID). Any design that cannot satisfy the capacity and Right-of-Way (ROW) requirement is deleted from future analysis. In stage three of the selection process, the alternative intersection designs selected for consideration are ranked and assessed based on the treatment purposes/stakeholders’ interests, which may likely include increasing mobility or safety. By identifying a primary parameter used to score or rank all the considered intersections, the alternative intersection selection tool would assist planners to compare different intersection designs and to describe the intersection performance comprehensively. The primary parameter should account for both mobility and safety at each of the intersections evaluated. For intersection mobility, the evaluation process relies on methodologies provided in the Highway Capacity Manual 2016. For the safety assessment, a safety evaluation procedure is also developed to provide an overall assessment of the safety performance at the evaluated intersection. A selection algorithm is then designed to rank all intersections based the intersection performance