231 research outputs found

    Low Complexity Multiplier-less Modified FRM Filter Bank using MPGBP Algorithm

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    The design of a low complexity multiplier-less narrow transition band filter bank for the channelizer of multi-standard software-defined radio (SDR) is investigated in this paper. To accomplish this, the modal filter and complementary filter in the upper and lower branches of the conventional Frequency Response Masking (FRM) architecture are replaced with two power-complementary and linear phase filter banks. Secondly, a new masking strategy is proposed to fully exploit the potential of the numerous spectra replicas produced by the interpolation of the modal filter, which was previously ignored in the existing FRM design. In this scheme, the two masking filters are appropriately modulated and alternately masked over the spectra replicas from 0 to 2π\pi, to generate even and odd channels. This Alternate Masking Scheme (AMS) increases the potency of the Modified FRM (ModFRM) architecture for the design of a computationally efficient narrow transition band uniform filter bank (termed as ModFRM-FB). Finally, by combining the adjoining ModFRM-FB channels, Non-Uniform ModFRM-FB (NUModFRM-FB) for extracting different communication standards in the SDR channelizer is created. To reduce the total power consumption of the architecture, the coefficients of the proposed system are made multiplier-less using the Matching Pursuits Generalized Bit-Planes (MPGBP) algorithm. In this method, filter coefficients are successively approximated using a dictionary of vectors to give a sum-of-power-of-two (SOPOT) representation. In comparison to all other general optimization techniques, such as genetic algorithms, the suggested design method stands out for its ease of implementation, requiring no sophisticated optimization or exhaustive search schemes. Another notable feature of the suggested approach is that, in comparison to existing methods, the design time for approximation has been greatly reduced. To further bring down the complexity, adders are reused in recurrent SOPOT terms using the Common Sub-expression Elimination (CSE) technique without compromising the filter performance

    Low Complexity Multiplier-less Modified FRM Filter Bank using MPGBP Algorithm

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    The design of a low complexity multiplier-less narrow transition band filter bank for the channelizer of multi-standard software-defined radio (SDR) is investigated in this paper. To accomplish this, the modal filter and complementary filter in the upper and lower branches of the conventional Frequency Response Masking (FRM) architecture are replaced with two power-complementary and linear phase filter banks. Secondly, a new masking strategy is proposed to fully exploit the potential of the numerous spectra replicas produced by the interpolation of the modal filter, which was previously ignored in the existing FRM design. In this scheme, the two masking filters are appropriately modulated and alternately masked over the spectra replicas from 0 to 2π\pi, to generate even and odd channels. This Alternate Masking Scheme (AMS) increases the potency of the Modified FRM (ModFRM) architecture for the design of a computationally efficient narrow transition band uniform filter bank (termed as ModFRM-FB). Finally, by combining the adjoining ModFRM-FB channels, Non-Uniform ModFRM-FB (NUModFRM-FB) for extracting different communication standards in the SDR channelizer is created. To reduce the total power consumption of the architecture, the coefficients of the proposed system are made multiplier-less using the Matching Pursuits Generalized Bit-Planes (MPGBP) algorithm. In this method, filter coefficients are successively approximated using a dictionary of vectors to give a sum-of-power-of-two (SOPOT) representation. In comparison to all other general optimization techniques, such as genetic algorithms, the suggested design method stands out for its ease of implementation, requiring no sophisticated optimization or exhaustive search schemes. Another notable feature of the suggested approach is that, in comparison to existing methods, the design time for approximation has been greatly reduced. To further bring down the complexity, adders are reused in recurrent SOPOT terms using the Common Sub-expression Elimination (CSE) technique without compromising the filter performance

    Design and Implementation of Complexity Reduced Digital Signal Processors for Low Power Biomedical Applications

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    Wearable health monitoring systems can provide remote care with supervised, inde-pendent living which are capable of signal sensing, acquisition, local processing and transmission. A generic biopotential signal (such as Electrocardiogram (ECG), and Electroencephalogram (EEG)) processing platform consists of four main functional components. The signals acquired by the electrodes are amplified and preconditioned by the (1) Analog-Front-End (AFE) which are then digitized via the (2) Analog-to-Digital Converter (ADC) for further processing. The local digital signal processing is usually handled by a custom designed (3) Digital Signal Processor (DSP) which is responsible for either anyone or combination of signal processing algorithms such as noise detection, noise/artefact removal, feature extraction, classification and compres-sion. The digitally processed data is then transmitted via the (4) transmitter which is renown as the most power hungry block in the complete platform. All the afore-mentioned components of the wearable systems are required to be designed and fitted into an integrated system where the area and the power requirements are stringent. Therefore, hardware complexity and power dissipation of each functional component are crucial aspects while designing and implementing a wearable monitoring platform. The work undertaken focuses on reducing the hardware complexity of a biosignal DSP and presents low hardware complexity solutions that can be employed in the aforemen-tioned wearable platforms. A typical state-of-the-art system utilizes Sigma Delta (Σ∆) ADCs incorporating a Σ∆ modulator and a decimation filter whereas the state-of-the-art decimation filters employ linear phase Finite-Impulse-Response (FIR) filters with high orders that in-crease the hardware complexity [1–5]. In this thesis, the novel use of minimum phase Infinite-Impulse-Response (IIR) decimators is proposed where the hardware complexity is massively reduced compared to the conventional FIR decimators. In addition, the non-linear phase effects of these filters are also investigated since phase non-linearity may distort the time domain representation of the signal being filtered which is un-desirable effect for biopotential signals especially when the fiducial characteristics carry diagnostic importance. In the case of ECG monitoring systems the effect of the IIR filter phase non-linearity is minimal which does not affect the diagnostic accuracy of the signals. The work undertaken also proposes two methods for reducing the hardware complexity of the popular biosignal processing tool, Discrete Wavelet Transform (DWT). General purpose multipliers are known to be hardware and power hungry in terms of the number of addition operations or their underlying building blocks like full adders or half adders required. Higher number of adders leads to an increase in the power consumption which is directly proportional to the clock frequency, supply voltage, switching activity and the resources utilized. A typical Field-Programmable-Gate-Array’s (FPGA) resources are Look-up Tables (LUTs) whereas a custom Digital Signal Processor’s (DSP) are gate-level cells of standard cell libraries that are used to build adders [6]. One of the proposed methods is the replacement of the hardware and power hungry general pur-pose multipliers and the coefficient memories with reconfigurable multiplier blocks that are composed of simple shift-add networks and multiplexers. This method substantially reduces the resource utilization as well as the power consumption of the system. The second proposed method is the design and implementation of the DWT filter banks using IIR filters which employ less number of arithmetic operations compared to the state-of-the-art FIR wavelets. This reduces the hardware complexity of the analysis filter bank of the DWT and can be employed in applications where the reconstruction is not required. However, the synthesis filter bank for the IIR wavelet transform has a higher computational complexity compared to the conventional FIR wavelet synthesis filter banks since re-indexing of the filtered data sequence is required that can only be achieved via the use of extra registers. Therefore, this led to the proposal of a novel design which replaces the complex IIR based synthesis filter banks with FIR fil-ters which are the approximations of the associated IIR filters. Finally, a comparative study is presented where the hybrid IIR/FIR and FIR/FIR wavelet filter banks are de-ployed in a typical noise reduction scenario using the wavelet thresholding techniques. It is concluded that the proposed hybrid IIR/FIR wavelet filter banks provide better denoising performance, reduced computational complexity and power consumption in comparison to their IIR/IIR and FIR/FIR counterparts

    Evolutionary design of digital VLSI hardware

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    Evolvable hardware platform for fault-tolerant reconfigurable sensor electronics

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    Energy efficient hardware acceleration of multimedia processing tools

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    The world of mobile devices is experiencing an ongoing trend of feature enhancement and generalpurpose multimedia platform convergence. This trend poses many grand challenges, the most pressing being their limited battery life as a consequence of delivering computationally demanding features. The envisaged mobile application features can be considered to be accelerated by a set of underpinning hardware blocks Based on the survey that this thesis presents on modem video compression standards and their associated enabling technologies, it is concluded that tight energy and throughput constraints can still be effectively tackled at algorithmic level in order to design re-usable optimised hardware acceleration cores. To prove these conclusions, the work m this thesis is focused on two of the basic enabling technologies that support mobile video applications, namely the Shape Adaptive Discrete Cosine Transform (SA-DCT) and its inverse, the SA-IDCT. The hardware architectures presented in this work have been designed with energy efficiency in mind. This goal is achieved by employing high level techniques such as redundant computation elimination, parallelism and low switching computation structures. Both architectures compare favourably against the relevant pnor art in the literature. The SA-DCT/IDCT technologies are instances of a more general computation - namely, both are Constant Matrix Multiplication (CMM) operations. Thus, this thesis also proposes an algorithm for the efficient hardware design of any general CMM-based enabling technology. The proposed algorithm leverages the effective solution search capability of genetic programming. A bonus feature of the proposed modelling approach is that it is further amenable to hardware acceleration. Another bonus feature is an early exit mechanism that achieves large search space reductions .Results show an improvement on state of the art algorithms with future potential for even greater savings

    Techniques for Efficient Implementation of FIR and Particle Filtering

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