Modified Lifting Scheme for DWT along with Parallel scanning Architecture 1

Abstract To overcome the inefficiencies in the JPEG standard and serve emerging areas of mobile and Internet communications, the new Lifting Scheme and processing element has been developed based on the principles of DWT. Previous DWT architectures are mostly based on the lift ing scheme/flipping structure where at least four pipelining stages were required for each multiplier or a large temporal buffer is needed. In this brief, modifications are made to the lifting scheme, and the intermediate results are recombined in the processing element and stored to get three number of pipelining stages and with reduced design complexity, computational time and to get the result in 2Dimensional image. Through optimizing the lifting scheme, Wu and Lin [10] implemented the parallel 2-D DWT. The design is a pipelined two-input/two-output architecture, and a 2×2 transposing module with four registers was developed. In addition, the critical path delay is one Tm. Nevertheless, it needs eight pipelining stages to complete the 1-D DWT and makes the total number of registers reach 22. The flipping structure is another important DWT architecture that was proposed by Huang et al. In this brief, further optimization on the processing element is proposed to overcome shortages in previous works and minimize sizes of the logic units and the memory without loss of the throughput. By recombining the intermediate results of the row and column transforms, the number of pipelining stages and registers is reduced, while keeping the critical path delay as Tm. In addition, a novel architecture is developed to implement the 2-D DWT based on the above modified scheme. The parallel scanning method is employed to reduce the computational time. As a result, our design achieves higher efficiency. The rest of this brief is organized as follows. Section II reviews the lifting scheme of the DWT in and Section III presents the proposed architecture for the 2-D DWT, and Section IV provides implementation results and comparisons with previous architectures. Conclusion is drawn in Section

Hardware implementation of daubechies wavelet transforms using folded AIQ mapping

The Discrete Wavelet Transform (DWT) is a popular tool in the field of image and video compression applications. Because of its multi-resolution representation capability, the DWT has been used effectively in applications such as transient signal analysis, computer vision, texture analysis, cell detection, and image compression. Daubechies wavelets are one of the popular transforms in the wavelet family. Daubechies filters provide excellent spatial and spectral locality-properties which make them useful in image compression. In this thesis, we present an efficient implementation of a shared hardware core to compute two 8-point Daubechies wavelet transforms. The architecture is based on a new two-level folded mapping technique, an improved version of the Algebraic Integer Quantization (AIQ). The scheme is developed on the factorization and decomposition of the transform coefficients that exploits the symmetrical and wrapping structure of the matrices. The proposed architecture is parallel, pipelined, and multiplexed. Compared to existing designs, the proposed scheme reduces significantly the hardware cost, critical path delay and power consumption with a higher throughput rate. Later, we have briefly presented a new mapping scheme to error-freely compute the Daubechies-8 tap wavelet transform, which is the next transform of Daubechies-6 in the Daubechies wavelet series. The multidimensional technique maps the irrational transformation basis coefficients with integers and results in considerable reduction in hardware and power consumption, and significant improvement in image reconstruction quality

A Pipeline VLSI Architecture for High-Speed Computation of the 1-D Discrete Wavelet Transform

In this paper, a scheme for the design of a high-speed pipeline VLSI architecture for the computation of the 1-D discrete wavelet transform (DWT) is proposed. The main focus of the scheme is on reducing the number and period of clock cycles for the DWT computation with little or no overhead on the hardware resources by maximizing the inter- and intrastage parallelisms of the pipeline. The interstage parallelism is enhanced by optimally mapping the computational load associated with the various DWT decomposition levels to the stages of the pipeline and by synchronizing their operations. The intrastage parallelism is enhanced by decomposing the filtering operation equally into two subtasks that can be performed independently in parallel and by optimally organizing the bitwise operations for performing each subtask so that the delay of the critical data path from a partial-product bit to a bit of the output sample for the filtering operation is minimized. It is shown that an architecture designed based on the proposed scheme requires a smaller number of clock cycles compared to that of the architectures employing comparable hardware resources. In fact, the requirement on the hardware resources of the architecture designed by using the proposed scheme also gets improved due to a smaller number of registers that need to be employed. Based on the proposed scheme, a specific example of designing an architecture for the DWT computation is considered. In order to assess the feasibility and the efficiency of the proposed scheme, the architecture thus designed is simulated and implemented on a field-programmable gate-array board. It is seen that the simulation and implementation results conform to the stated goals of the proposed scheme, thus making the scheme a viable approach for designing a practical and realizable architecture for real-time DWT computation

A Pipeline VLSI Architecture for Fast Computation of the 2-D Discrete Wavelet Transform

In this paper, a scheme for the design of a high-speed pipeline VLSI architecture for the computation of the 2-D discrete wavelet transform (DWT) is proposed. The main focus in the development of the architecture is on providing a high operating frequency and a small number of clock cycles along with an efficient hardware utilization by maximizing the inter-stage and intra-stage computational parallelism for the pipeline. The inter-stage parallelism is enhanced by optimally mapping the computational task of multi decomposition levels to the stages of the pipeline and synchronizing their operations. The intra-stage parallelism is enhanced by dividing the 2-D filtering operation into four subtasks that can be performed independently in parallel and minimizing the delay of the critical path of bit-wise adder networks for performing the filtering operation. To validate the proposed scheme, a circuit is designed, simulated, and implemented in FPGA for the 2-D DWT computation. The results of the implementation show that the circuit is capable of operating with a maximum clock frequency of 134 MHz and processing 1022 frames of size 512 × 512 per second with this operating frequency. It is shown that the performance in terms of the processing speed of the architecture designed based on the proposed scheme is superior to those of the architectures designed using other existing schemes, and it has similar or lower hardware consumption

DESIGN AND IMPLEMENTATION OF LIFTING BASED DAUBECHIES WAVELET TRANSFORMS USING ALGEBRAIC INTEGERS

Over the past few decades, the demand for digital information has increased drastically. This enormous demand poses serious difficulties on the storage and transmission bandwidth of the current technologies. One possible solution to overcome this approach is to compress the amount of information by discarding all the redundancies. In multimedia technology, various lossy compression techniques are used to compress the raw image data to facilitate storage and to fit the transmission bandwidth. In this thesis, we propose a new approach using algebraic integers to reduce the complexity of the Daubechies-4 (D4) and Daubechies-6 (D6) Lifting based Discrete Wavelet Transforms. The resulting architecture is completely integer based, which is free from the round-off error that is caused in floating point calculations. The filter coefficients of the two transforms of Daubechies family are individually converted to integers by multiplying it with value of 2x, where, x is a random value selected at a point where the quantity of losses is negligible. The wavelet coefficients are then quantized using the proposed iterative individual-subband coding algorithm. The proposed coding algorithm is adopted from the well-known Embedded Zerotree Wavelet (EZW) coding. The results obtained from simulation shows that the proposed coding algorithm proves to be much faster than its predecessor, and at the same time, produces good Peak Signal to Noise Ratio (PSNR) at very low bit rates. Finally, the two proposed transform architectures are implemented on Virtex-E Field Programmable Gate Array (FPGA) to test the hardware cost (in terms of multipliers, adders and registers) and throughput rate. From the synthesis results, we see that the proposed algorithm has low hardware cost and a high throughput rate

リフティング構造を利用した非分離型ウェーブレット変換のノイズ低減に関する研究

国立大学法人長岡技術科学大