Fast structured design of VLSI circuits

technical reportWe believe that a structured, user-friendly, cost-effective tool for rapid implementation of VLSI circuits which encourages students to participate directly in research projects are the key components in digital integrated circuit (IC) education. In this paper, we introduce our VLSI education activities, with t h e emphasis on t h e presentation of Path Programmable Logic (PPL) design methodology, in addition to a short description of a representative student project. Students using PPL are able to implement MOS or GaAs VLSI circuits with several thousands to over 100,000 transistors in a few weeks. They have designed and built numerous VLSI architectures and computer systems which play an influential role in various research areas. Our educational activities and the Utah Annual Student VLSI Design Contest supported by over a dozen leading American firms have attracted multiple university involvement in recent years

Innovative teaching of IC design and manufacture using the Superchip platform

In this paper we describe how an intelligent chip architecture has allowed a large cohort of undergraduate students to be given effective practical insight into IC design by designing and manufacturing their own ICs. To achieve this, an efficient chip architecture, the “Superchip”, has been developed, which allows multiple student designs to be fabricated on a single IC, and encapsulated in a standard package without excessive cost in terms of time or resources. We demonstrate how the practical process has been tightly coupled with theoretical aspects of the degree course and how transferable skills are incorporated into the design exercise. Furthermore, the students are introduced at an early stage to the key concepts of team working, exposure to real deadlines and collaborative report writing. This paper provides details of the teaching rationale, design exercise overview, design process, chip architecture and test regime

The Potential of Establishing Technology Computer Aided Design Industry: Africa - Sudan As a Case-Study

Very-Large-Scale-Integration (VLSI) Integrated-Circuit (IC) designs have steadily grown in their capacity and complexity through the years. The need for technology simulations using technology computer-aided-design (TCAD) tools have become an essential part of design success. The TCAD simulations facilitate process optimization, highlight device performance tradeoffs, enable worst case analysis, and reveal device defects and weakness. Microelectronics higher education in African universities focuses mainly on the chip/circuit design instruction. Virtually little or no emphasis is applied to grow students TCAD simulation skills. This paper discusses the potential of African educational institutes of becoming the supplier of qualified TCAD simulation engineers for future African IC industry and/or worldwide VLSI job market. The African universities are encouraged to emphasize on establishing frameworks that would include TCAD simulation research and development into their curriculums and motivate students to venture the VLSI design and automation fields. This would enable African graduates to exploit the microelectronics job market worldwide and establish TCAD industries within Africa to industrialize African job market

PERFORMANCE ANALYSIS OF FINFET BASED INVERTER, NAND AND NOR CIRCUITS AT 10 NM ,7 NM AND 5 NM NODE TECHNOLOGIES

Advancement in the semiconductor industry has transformed modern society. A miniaturization of a silicon transistor is continuing following Moore’s empirical law. The planar metal-oxide semiconductor field effect transistor (MOSFET) structure has reached its limit in terms of technological node reduction. To ensure the continuation of CMOS scaling and to overcome the Short Channel Effect (SCE) issues, a new MOS structure known as Fin field-effect transistor (FinFET) has been introduced and has led to significant performance enhancements.This paper presents a comparative study of CMOS gates designed with FinFET 10 nm, 7 nm and 5 nm technology nodes. Electrical parameters like the maximum switching current ION, the leakage current IOFF, and the performance ratio ION/IOFF for N and P FinFET with different nodes are presented in this simulation.The aim and the novelty  of this paper is to extract the operating frequency for CMOS circuits using Quantum and Stress effects implemented in the Spice parameters on the latest Microwind software. The simulation results show a fitting with experimental data  for FinFET N and P 10 nm strctures using quantum correction. Finally, we have demonstrate that FinFET 5 nm can reach a minimum time delay of  td=1.4 ps for CMOS NOT gate and td=1 ps  for CMOS NOR gate to improve Integrated Circuits IC