Analysis and Comparison of Different Multiplier

Multiplication is one of the important parameter in various digital applications such as in digital signal processor, microprocessor so in this paper firstly we analyse various 4*4 multiplier circuit and then analyses various 12*12 bit multiplier circuit. After then their parameters i.e area, power and delay are analyzed. All these multiplier are designed in Verilog language and synthesized on Xilinx ISE simulator and using cadence RTL schematic respectively. Multipliers included in this paper are Array multiplier, Radix-4 multiplier, Radix-8 multiplier, Wallace Multiplier and Conventional multiplier. On comparison it is found that for 4*4 and 12*12 multiplier, array multiplier have highest delay but have less power consumption while Booth multiplier(Radix-4) is having high speed with moderate power consumption

Implementación de redes neuronales utilizando dispositivos lógicos programables

From the beginning of the computational revolution there was interest for the intelligent machines. After the failure of the searching methods or Artificial Intelligence applied to real problems, a new approach, Computational Intelligence, recaptured the road basing on structures copied from nature. The (artificial) neural networks emulate in a simplified way the operation of the biological networks. Research has been directed primarily to computer simulation of the proposed algorithms, which moves away from the real behavior of the biological neurons. This article shows a development of a system for designing, simulating, creating, and interacting with neural netwoks implemented in a physical device, to come closer to the biological concept. The target device, a FPGA, is an arrangement of logical elements, whose interconnection points can be programmed, wich better models the evolutionof a biological brain.Desde el comienzo de la revolución computacional hubo interés por las máquinas inteligentes. Después del fracaso de los métodos de búsqueda de inteligencia artificial aplicados a problemas reales, un nuevo enfoque: inteligencia computacional retomó el camino basándose en estructuras copiadas de la naturaleza. Las redes neuronales (artificiales) emulan de manera simplificada el funcionamiento de las redes biológicas. La investigación ha estado dirigida primordialmente a simulación en computador de los algoritmos que se proponen, lo que se aleja del comportamiento real de las neuronas biológicas. Este artículo muestra un desarrollo en el que se implementó un sistema para diseñar, simular, crear e interactuar con redes neuronales en un dispositivo físico, para acercarse al concepto biológico. El dispositivo de trabajo (un FPGA) es un arreglo de elemento lógicos, cuyos puntos de interconexión pueden ser programados, lo que modela mejor la evolución de un cerebr biológico

Multiplierless CSD techniques for high performance FPGA implementation of digital filters.

I leverage FastCSD to develop a new, high performance iterative multiplierless structure based on a novel real-time CSD recoding, so that more zero partial products are introduced. Up to 66.7% zero partial products occur compared to 50% in the traditional modified Booth's recoding. Also, this structure reduces the non-zero partial products to a minimum. As a result, the number of arithmetic operations in the carry-save structure is reduced. Thus, an overall speed-up, as well as low-power consumption can be achieved. Furthermore, because the proposed structure involves real time CSD recoding and does not require a fixed value for the multiplier input to be known a priori, the proposed multiplier can be applied to implement digital filters with non-fixed filter coefficients, such as adaptive filters.My work is based on a dramatic new technique for converting between 2's complement and CSD number systems, and results in high-performance structures that are particularly effective for implementing adaptive systems in reconfigurable logic.My research focus is on two key ideas for improving DSP performance: (1) Develop new high performance, efficient shift-add techniques ("multiplierless") to implement the multiply-add operations without the need for a traditional multiplier structure. (2) There is a growing trend toward design prototyping and even production in FPGAs as opposed to dedicated DSP processors or ASICs; leverage this trend synergistically with the new multiplierless structures to improve performance.Implementation of digital signal processing (DSP) algorithms in hardware, such as field programmable gate arrays (FPGAs), requires a large number of multipliers. Fast, low area multiply-adds have become critical in modern commercial and military DSP applications. In many contemporary real-time DSP and multimedia applications, system performance is severely impacted by the limitations of currently available speed, energy efficiency, and area requirement of an onboard silicon multiplier.I also introduce a new multi-input Canonical Signed Digit (CSD) multiplier unit, which requires fewer shift/add/subtract operations and reduced CSD number conversion overhead compared to existing techniques. This results in reduced power consumption and area requirements in the hardware implementation of DSP algorithms. Furthermore, because all the products are produced simultaneously, the multiplication speed and thus the throughput are improved. The multi-input multiplier unit is applied to implement digital filters with non-fixed filter coefficients, such as adaptive filters. The implementation cost of these digital filters can be further reduced by limiting the wordlength of the input signal with little or no sacrifice to the filter performance, which is confirmed by my simulation results. The proposed multiplier unit can also be applied to other DSP algorithms, such as digital filter banks or matrix and vector multiplications.Finally, the tradeoff between filter order and coefficient length in the design and implementation of high-performance filters in Field Programmable Gate Arrays (FPGAs) is discussed. Non-minimum order FIR filters are designed for implementation using Canonical Signed Digit (CSD) multiplierless implementation techniques. By increasing the filter order, the length of the coefficients can be decreased without reducing the filter performance. Thus, an overall hardware savings can be achieved.Adaptive system implementations require real-time conversion of coefficients to Canonical Signed Digit (CSD) or similar representations to benefit from multiplierless techniques for implementing filters. Multiplierless approaches are used to reduce the hardware and increase the throughput. This dissertation introduces the first non-iterative hardware algorithm to convert 2's complement numbers to their CSD representations (FastCSD) using a fixed number of shift and logic operations. As a result, the power consumption and area requirements required for hardware implementation of DSP algorithms in which the coefficients are not known a priori can be greatly reduced. Because all CSD digits are produced simultaneously, the conversion speed and thus the throughput are improved when compared to overlap-and-scan techniques such as Booth's recoding