Dynamically variable step search motion estimation algorithm and a dynamically reconfigurable hardware for its implementation

Motion Estimation (ME) is the most computationally intensive part of video compression and video enhancement systems. For the recently available High Definition (HD) video formats, the computational complexity of De full search (FS) ME algorithm is prohibitively high, whereas the PSNR obtained by fast search ME algorithms is low. Therefore, ill this paper, we present Dynamically Variable Step Search (DVSS) ME algorithm for Processing high definition video formats and a dynamically reconfigurable hardware efficiently implementing DVSS algorithm. The architecture for efficiently implementing DVSS algorithm. The simulation results showed that DVSS algorithm performs very close to FS algorithm by searching much fewer search locations than FS algorithm and it outperforms successful past search ME algorithms by searching more search locations than these algorithms. The proposed hardware is implemented in VHDL and is capable, of processing high definition video formats in real time. Therefore, it can be used in consumer electronics products for video compression, frame rate up-conversion and de-interlacing(1)

Motion estimation based frame rate conversion hardware designs

Frame Rate Up-Conversion (FRC) is the conversion of a lower frame rate video signal to a higher frame rate video signal. FRC algorithms using Motion Estimation (ME) obtain better quality results. Among the block matching ME algorithms, Full Search (FS) achieves the best performance since it searches all search locations in a given search range. However, its computational complexity, especially for the recently available High Definition (HD) video formats, is very high. Therefore, in this thesis, we proposed new ME algorithms for real-time processing of HD video and designed efficient hardware architectures for implementing these ME algorithms. These algorithms perform very close to FS by searching much fewer search locations than FS algorithm. We implemented the proposed hardware architectures in VHDL and mapped them to a Xilinx FPGA. ME for FRC requires finding the true motion among consecutive frames. In order to find the true motion, Vector Median Filter (VMF) is used to smooth the motion vector field obtained by block matching ME. However, VMFs are difficult to implement in real-time due to their high computational complexity. Therefore, in this thesis, we proposed several techniques to reduce the computational complexity of VMFs by using data reuse methodology and by exploiting the spatial correlations in the vector field. In addition, we designed an efficient VMF hardware including the computation reduction techniques exploiting the spatial correlations in the motion vector field. We implemented the proposed hardware architecture in Verilog and mapped it to a Xilinx FPGA. ME based FRC requires interpolation of frames using the motion vectors found by ME. Frame interpolation algorithms also have high computational complexity. Therefore, in this thesis, we proposed a low cost hardware architecture for real-time implementation of frame interpolation algorithms. The proposed hardware architecture is reconfigurable and it allows adaptive selection of frame interpolation algorithms for each Macroblock. We implemented the proposed hardware architecture in VHDL and mapped it to a low cost Xilinx FPGA

書き換え可能なゲートアレイを用いた無作為抽出法に基づく実時間画像処理に関する研究

長崎大学学位論文 学位記番号:博(工)甲第53号 学位授与年月日:平成30年3月20日Nagasaki University (長崎大学)課程博

Development of novel ultrasound techniques for imaging and elastography. From simulation to real-time implementation

Ultrasound techniques offer many advantages, in terms of ease of realization and patients’ safety. The availability of suitable hardware and software tools is condicio sine qua non for new methods testing. This PhD project addresses medical ultrasound signal processing and seeks to achieve two scientific goals: the first is to contribute to the development of an ultrasound research platform, while the second is introducing and validating, through this platform, non-standard methods. During the thesis, the capabilities of the system were improved by creating advanced software tools, such as acoustic field simulators, and by developing echo-signals elaboration programs. In particular, a novel technique for quasi-static elastography was developed, in-vitro tested and implemented in real-time

Acceptable load carriage for primary school girls

Randomized six primary school girls aged between 9 to 10 years old completed this study at the Motion Analysis Laboratory, Department of Biomedical Engineering, University of Malaya, Malaysia. Three different loads were used (10, 15 and 20 of their body weight) and 0 was used as control during level walking. The data obtained, both kinetics and kinematics, were analyzed using the Peak Motus® 7.2.4 software from PEAK Performance Technologies® and SPSSO version 12.0 software. The results indicated that the peak ground reaction forces increased with increasing backpack loads. The hip and knee flexion/extension increased as the loads increased. The stride length and walking speed decreased, while the cadence showed no significant difference (P>0.05). If the trunk angle is taken as the criterion to determine acceptable backpack loads for children, these loads should not exceed 10 of the children's body weight. © EuroJournals Publishing, Inc. 2006