Controlling the harmonic conversion efficiency in semiconductor superlattices by interface roughness design

In semiconductor superlattices, when Bragg oscillating electrons interact with an input electromagnetic field, frequency multiplication is possible. An ideal superlattice has a purely antisymmetric voltage current response and can thus produce only odd harmonics. However, real world superlattices can also have even harmonic response and that increases the range of possible output frequencies. These effects have been recently explained with a predictive model that combines an Ansatz solution for the Boltzmann Equation with a Nonequilibrium Green's Functions approach. This predictive tool, coupled with recent progress on GHz input sources, support the growing interest in developing compact room temperature devices that can operate from the GHz to the THz range. The natural question to ask is what efficiencies can be expected. This paper addresses this issue by investigating power-conversion efficiency in irradiated semiconductor superlattices. Interface imperfections are consistently included in the theory and they strongly influence the power output of both odd and even harmonics. Good agreement is obtained for predicted odd harmonic outputs with experimental data for a wide frequency range. The intrinsic conversion efficiency used is based on the estimated amplitude of the input field inside the sample and thus independent of geometrical factors that characterize different setups. The method opens the possibility of designing even harmonic output power by controlling the interface quality

Planar Heterostructure Barrier Varactor Diodes for Millimetre Wave Applications

This thesis deals with fabrication, characterisation and modelling of the Heterostructure Barrier Varactor (HBV) diode and its use in frequency multiplier applications. Different aspects of material structures and frequency multipliers are described. The aim of the work presented is to develop design methods and processes to fabricate state-of-the-art planar HBVs and multipliers in the millimetre and submillimetre wave length region.<p /> Results from AlGaAs HBV frequency tripler measurements are presented. Simulations and cooled measurements show that excessive conduction current due to self-heating degrades the multiplier efficiency. A new design of planar GaAs-based HBVs with reduced thermal resistance and series resistance have been fabricated. A state-of-the-art performance of 4,8% efficiency and an output power of 4 mW at 246 GHz was achieved.<p /> A novel fabrication process where HBV diodes are fabricated on a copper substrate is proposed. This reduces thermal resistance and parasitic resistance without degrading the electrical characteristics.<p /> A 141 GHz quasi-optical HBV tripler is presented. A peak flange-to-flange efficiency of 8% and an output power of 11,5 mW was achieved.<p /> Different III-V material systems for HBVs have been tested. The results of lattice matched and pseudomorphic GaAs/AlGaAs, InGaAs/InAlAs, InAs/AlSb and phosphide containing materials for HBVs are presented. The state-of-the-art material for millimetre and submillimetre wave HBVs is the In_0,53GaAs/In_0,52AlAs system with a thin AlAs layer (30 Å) in the middle of the barrier.<p /> Both simple analytical models and a self-consistent Poisson/Schroedinger approach are used to predict and optimise HBV diodes. Finally, a simple quick-design method for calculation of optimum embedding impedances, optimum conversion efficiency and pump power for HBV triplers are presented

Lower-order compensation chain threshold-reduction technique for multi-stage voltage multipliers

This paper presents a novel threshold-compensation technique for multi-stage voltage multipliers employed in low power applications such as passive and autonomous wireless sensing nodes (WSNs) powered by energy harvesters. The proposed threshold-reduction technique enables a topological design methodology which, through an optimum control of the trade-off among transistor conductivity and leakage losses, is aimed at maximizing the voltage conversion efficiency (VCE) for a given ac input signal and physical chip area occupation. The conducted simulations positively assert the validity of the proposed design methodology, emphasizing the exploitable design space yielded by the transistor connection scheme in the voltage multiplier chain. An experimental validation and comparison of threshold-compensation techniques was performed, adopting 2N5247 N-channel junction field effect transistors (JFETs) for the realization of the voltage multiplier prototypes. The attained measurements clearly support the effectiveness of the proposed threshold-reduction approach, which can significantly reduce the chip area occupation for a given target output performance and ac input signal

The road to fully integrated DC-DC conversion via the switched-capacitor approach

This paper provides a perspective on progress toward realization of efficient, fully integrated dc-dc conversion and regulation functionality in CMOS platforms. In providing a comparative assessment between the inductor-based and switched-capacitor approaches, the presentation reviews the salient features in effectiveness in utilization of switch technology and in use and implementation of passives. The analytical conclusions point toward the strong advantages of the switched-capacitor (SC) approach with respect to both switch utilization and much higher energy densities of capacitors versus inductors. The analysis is substantiated with a review of recently developed and published integrated dc-dc converters of both the inductor-based and SC types. © 2012 IEEE

Heterostructure-Barrier-Varactor Design

In this paper, we propose a simple set of accurate frequency-domain design equations for calculation of optimum embedding impedances, optimum input power, bandwidth, and conversion efficiency of heterostructure-barrier-varactor (HBV) frequency triplers. A set of modeling equations for harmonic balance simulations of HBV multipliers are also given. A 141-GHz quasi-optical HBV tripler was designed using the method and experimental results show good agreement with the predicted results

System-level design tool for switched capacitor DC-DC energy scavenging converters

This thesis deals with the system modelling and design of a Switched Capac- itor DC-DC (SC DC-DC) nano-power converter in Complementary Metal Oxide Semiconductor (CMOS) technology for energy harvesting applications. First of all, after a critical evaluation on the whole Integrated Circuit (IC) system structure, a Python script has been created in order to accurately analyse any system analytical behaviours before instantiating and running the Cadence usual simulations. The code is an upgrade with respect to a pre-existing one ([1]): several com- parisons are listed and explained to show the differences between the two, as well as stressing on our new dedicated features. In order to validate the model on the code, then, a feasibility study has been performed with a 180 nm United Microelectronics Corporation (UMC) technol- ogy process in the Cadence Virtuoso design suite. Good results let us state its reliability in being used both for the most of SC DC-DC architectures pre-design analysis and post-design verification: a full design space exploration shows how to use the script. Finally, the SC DC-DC circuit D for bluetooth applications that we present uses the Taiwan Semiconductor Manufacturing Company (TSMC) 55 nm technol- ogy process and its design has been mostly realized by Luca Intaschi, during his PhD, and Francesco Dalena from Dialog Semiconductor in Livorno. The circuit D converter is meant to be part of a sensor node (that needs to survive in total absence of battery recharge) supplied by a Thermo Electric Generator (TEG) which guarantees a very low input voltage to the system of about 0.2

Models predicting the performance of IC component or PCB channel during electromagnetic interference

This dissertation is composed of three papers, which cover the prediction of the characteristics of jitter due to crosstalk and due to simultaneous switching noise, and covers susceptibility of delay locked loop (DLL) to electromagnetic interference. In the first paper, an improved tail-fit de-convolution method is proposed for characterizing the impact of deterministic jitter in the presence of random jitter. A Wiener filter de-convolution method is also presented for extracting the characteristics of crosstalk induced jitter from measurements of total jitter made when the crosstalk sources were and were not present. The proposed techniques are shown to work well both in simulations and in measurements of a high-speed link. In the second paper, methods are developed to predict the statistical distribution of timing jitter due to dynamic currents drawn by an integrated circuit (IC) and the resulting power supply noise on the PCB. Distribution of dynamic currents is found through vectorless methods. Results demonstrate the approach can rapidly determine the average and standard deviation of the power supply noise voltage and the peak jitter within 5~15% error, which is more than sufficient for predicting the performance impact on integrated circuits. In the third paper, a model is developed to predict the susceptibility of a DLL to electromagnetic noise on the power supply. With the proposed analytical noise transfer function, peak to peak jitter and cycle to cycle jitter at the DLL output can be estimated, which can be use to predict when soft failures will occur and to better understand how to fix these failures. Simulation and measurement results demonstrate the accuracy of the DLL delay model. --Abstract, page iv

Characteristics and performance of several mass spectrometer residual gas analyzers

The operation and properties of various mass-spectrometer residual gas analyzers for use in vacuum measurements were analyzed in terms of efficiencies of ion extraction, ion separation and transmission, and ion collection. Types of instruments studied were magnetic sector, omegatron, quadrupole, and monopole. Experimental results presented include absolute sensitivity to argon, relative sensitivity to 10 gases, and cracking patterns for these gases. It is shown that the properties are strongly dependent on instrument range, resolution, and the particular voltages, currents, or field intensities used to control the instrument

Study of Critical Heat Flux and Two-Phase Pressure Drop Under Reduced Gravity

The design of the two-phase flow systems which are anticipated to be utilized in future spacecraft thermal management systems requires a knowledge of two-phase flow and heat transfer phenomena in reduced gravities. This program was funded by NASA headquarters in response to NRA-91-OSSA-17 and was managed by Lewis Research Center. The main objective of this program was to design and construct a two-phase test loop, and perform a series of normal gravity and aircraft trajectory experiments to study the effect of gravity on the Critical Heat Flux (CHF) and onset of instability. The test loop was packaged on two aircraft racks and was also instrumented to generate data for two-phase pressure drop. The normal gravity tests were performed with vertical up and downflow configurations to bound the effect of gravity on the test parameters. One set of aircraft trajectory tests was performed aboard the NASA DC-9 aircraft. These tests were mainly intended to evaluate the test loop and its operational performance under actual reduced gravity conditions, and to produce preliminary data for the test parameters. The test results were used to demonstrate the applicability of the normal gravity models for prediction of the two-phase friction pressure drop. It was shown that the two-phase friction multipliers for vertical upflow and reduced gravity conditions can be successfully predicted by the appropriate normal gravity models. Limited critical heat flux data showed that the measured CHF under reduced gravities are of the same order of magnitude as the test results with vertical upflow configuration. A simplified correlation was only successful in predicting the measured CHF for low flow rates. Instability tests with vertical upflow showed that flow becomes unstable and critical heat flux occurs at smaller powers when a parallel flow path exists. However, downflow tests and a single reduced gravity instability experiment indicated that the system actually became more stable with a parallel single-phase flow path. Several design modifications have been identified which will improve the system performance for generating reduced gravity data. The modified test loop can provide two-phase flow data for a range of operating conditions and can serve as a test bed for component evaluation