Survey of traffic control schemes and error control schemes for ATM networks

Among the techniques proposed for B-ISDN transfer mode, ATM concept is considered to be the most promising transfer technique because of its flexibility and efficiency. This paper surveys and reviews a number of topics related to ATM networks. Those topics cover congestion control, provision of multiple classes of traffic, and error control. Due to the nature of ATM networks, those issues are far more challenging than in conventional networks. Sorne of the more promising solutions to those issues are surveyed, and the corresponding results on performance are summarized. Future research problems in ATM protocol aspect are also presented

Electronic and photonic switching in the atm era

Broadband networks require high-capacity switches in order to properly manage large amounts of traffic fluxes. Electronic and photonic technologies are being used to achieve this objective both allowing different multiplexing and switching techniques. Focusing on the asynchronous transfer mode (ATM), the inherent different characteristics of electronics and photonics makes different architectures feasible. In this paper, different switching structures are described, several ATM switching architectures which have been recently implemented are presented and the implementation characteristics discussed. Three diverse points of view are given from the electronic research, the photonic research and the commercial switches. Although all the architectures where successfully tested, they should also follow different market requirements in order to be commercialised. The characteristics are presented and the architectures projected over them to evaluate their commercial capabilities.Peer ReviewedPostprint (published version

Survey of congestion control techniques for an ATM network

The emerging broadband integrated services digital network is expected to adopt ATM (Asynchronous Transfer Mode) as the transport network. This new network must support several classes of service with varying delay and loss requirements. It must also operate with link speeds in the hundreds of megabits per second and be scalable up to potential link speeds on the order of gigabits per second. The requirements to support multiple services and high speed make the congestion control in an ATM network difficult. This paper reviews sorne of the techniques for prevention and control of congestion in an ATM network

Performance study of voice over frame relay : a thesis presented in partial fulfilment of the requirements for the degree of Master of Engineering in Information Engineering, Massey University, Albany, New Zealand

Frame Relay (FR) represents an important paradigm shift in modern telecommunication. This technology is beginning to evolve from data only application to broad spectrum of multimedia users and potential to provide end users with cost effective transport of voice traffic for intra office communication. In this project the recent development in voice communication over Frame relay is investigated. Simulations were carried out using OPNET, a powerful simulation software. Following the simulation model, a practical design of the LAN-to-LAN connectivity experiment was also done in the Net Lab. From the results of the simulation, Performance measures such as delay, jitter, and throughput are reported. It is evident from the results that real-time voice or video across a frame relay network can provide acceptable performance

A logic-level simulation of the ATMSWITCH : a thesis presented in partial fulfilment of the requirements for the degree of Master of Science in Computer Science at Massey University

ATM networks are intended to provide a "one-size-fits-all" solution to a variety of data communication needs, from low speed, delay-insensitive to high-speed, delay-intolerant. The basic ATM protocol certainly delivers traffic within this broad range, but it does not address the quality of service requirements associated with the various type of traffic. The ATMSW1TCH is designed to use two different mechanisms to provide the quality of service for the various type of traffic. It treats the cells according to their connected virtual channel type and services them as predefined scheme. The ATMSWITCH architecture is a shared-memory and output buffer strategy switch. The switch has been designed much of buffer location and identification can occur in parallel with the 12ns read/write cycle time required to buffer the cell data. The problem is essentially one of design circuitry so that buffer location and identification are as short as possible. The present project has therefore been intended to measure the number of clock cycles required to perform the buffer maintenance activities, and to determine whether the logic speed required to fit this number of clock cycles into the 12ns window is feasible using current technology. The simulated result and timing analysis shows that 10 clock cycles are required during 12ns buffer read and write time, and a reasonable clock speed is 1.2ns per clock cycle

Effects of Voice Compression on the Operation of aN-ISDN/B-ISDN IWF

The significant widespread of N-ISD , which has recently gained momentum, will make it hard for the emerging B-ISD whether to ignore its presence or to phase it out and replace it in the near foreseen future. Consequently, the ATM of the interoperability specification CES-IS V2.0 (af-vtoa-0078.000), which defines emulation standards for circuit characteristics of constant bit-rate (CBR) traffic within ATM. A critical attribute of a circuit emulation service (CES) is to achieve a performance comparable to that are still pending will be addressed. Special interest will be given to devising methods that will enable voice, which is a size able component of the current N-ISD traffic, to be carried efficiently over ATM network. First, a multiplexing technique for voice sources will be presented. Then, assuming that speech silence detection is being used, a technique for dealing with the partially filled cells wil be suggested, analyzed, and then simulated. The results will be then presented and analyzed, followed by conclusions and suggestions

Dynamic bandwidth allocation in ATM networks

Includes bibliographical references.This thesis investigates bandwidth allocation methodologies to transport new emerging bursty traffic types in ATM networks. However, existing ATM traffic management solutions are not readily able to handle the inevitable problem of congestion as result of the bursty traffic from the new emerging services. This research basically addresses bandwidth allocation issues for bursty traffic by proposing and exploring the concept of dynamic bandwidth allocation and comparing it to the traditional static bandwidth allocation schemes