An analog integrated circuit design laboratory

We present the structure of an analog integrated circuit design laboratory to instruct at both, senior undergraduate and entry graduate levels. The teaching material includes: a laboratory manual with analog circuit design theory, pre-laboratory exercises and circuit design specifications; a reference web page with step by step instructions and examples; the use of mathematical tools for automation and analysis; and state of the art CAD design tools in use by industry. Upon completion of the course, the students have skills for an entry level analog designer position

Development of a laboratory course in power electronic control circuitry based on a PWM buck controller

Thesis (M. Eng. and S.B.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2006.Includes bibliographical references (leaf 153).Due to the constraints on time and resources within the typical electrical engineering curriculum, it is difficult for students to obtain Integrated Circuit design experience prior to entering industry. This project establishes the foundation for a new laboratory course in power electronics and analog circuit design. There is an introduction to power electronics, particularly the buck converter, and several basic analog circuit building blocks are introduced. A process consisting of circuit design, simulation, construction, and evaluation is developed to provide students with an introduction to Integrated Circuit design. A peak current mode PWM controller for a buck converter is developed to illustrate the fundamental power electronic and analog circuit concepts that are presented.by Candace N. Wilson.M.Eng.and S.B

0.5V 3rd-order Tunable gm-C Filter

This paper proposes a 3rd-order gm-C filter that operates with the extremely low voltage supply of 0.5V. The employed transconductor is capable for operating in an extremely low voltage power supply environment. A benefit offered by the employed transconductor is that the filter’s cut-off frequency can be tuned, through a dc control current, for relatively large ranges. The filter structure was designed using normal threshold transistors of a triple-well 0.13μm CMOS process and is operated under a 0.5V supply voltage; its behavior has been evaluated through simulation results by utilizing the Analog Design Environment of the Cadence software

Hands-on Learning in Multiple Courses in Electrical and Computer Engineering

It has been reported that persistence rate of engineering students is relatively low. Several new pedagogical paradigms have been proposed to improve engineering education, such as the use of “hands-on” tools to change the learning style in the engineering classroom to more engaging teaching pedagogies. An approach that is being used to engage and retain electrical and computer engineering students is the Analog Discovery board (ADB). The paper describes the hands-on learning experiences of students who used the ADB in multiple courses. The paper discusses (i) the various laboratory experiments and class projects performed by the students, (ii) the knowledge and skills learnt by the students and (iii) the lessons learnt by the instructors while introducing ADB into freshman and junior level courses in the electrical and computer engineering. Preliminary data indicate that students are benefiting from the use of the ADB. Students report increases in their interest in subject content, motivation to learn, and confidence in their ability to learn.Cockrell School of Engineerin

Second-order neural core for bioinspired focal-plane dynamic image processing in CMOS

Based on studies of the mammalian retina, a bioinspired model for mixed-signal array processing has been implemented on silicon. This model mimics the way in which images are processed at the front-end of natural visual pathways, by means of programmable complex spatio-temporal dynamic. When embedded into a focal-plane processing chip, such a model allows for online parallel filtering of the captured image; the outcome of such processing can be used to develop control feedback actions to adapt the response of photoreceptors to local image features. Beyond simple resistive grid filtering, it is possible to program other spatio-temporal processing operators into the model core, such as nonlinear and anisotropic diffusion, among others. This paper presents analog and mixed-signal very large-scale integration building blocks to implement this model, and illustrates their operation through experimental results taken from a prototype chip fabricated in a 0.5-μm CMOS technology.European Union IST 2001 38097Ministerio de Ciencia y Tecnología TIC 2003 09817 C02 01Office of Naval Research (USA) N00014021088

A Multiproject Chip Approach to the Teaching of Analog MOS LSI and VLSI

Multiproject chip implementation has been used in teaching analog MOS circuit design. After having worked with computer simulation and layout aids in homework problems, students designed novel circuits including several high performance op amps, an A/D converter, a switched capacitor filter, a 1 K dynamic RAM, and a variety of less conventional MOS circuits such as a VII converter, an AC/DC converter, an AM radio receiver, a digitally-controlled analog signal processor, and on-chip circuitry for measuring transistor capacitances. These circuits were laid out as part of an NMOS multiproject chip. Several of the designs exhibit a considerable degree of innovation; fabrication pending, computer simulation shows that some may be pushing the state of the art. Several designs are of interest to digital designers; in fact, the course has provided knowledge and technique needed for detailed digital circuit design at the gate level

Automation of the Continuous Coagulation Monitor

The development of automation in the past 50 years has paralleled the accelerating growth of today’s vast technological society. Automatic control systems are indispensable extensions of man\u27s brain that enable him to monitor and regulate his complex environment. The principles of automatic control have a wide range of applications and interests in virtually every scientific field. The need for automatic control systems in vital applications of environmental engineering is both real and urgent. Extensive pollution has resulted in unavoidable water re-use and in the inevitable establishment of stringent effluent standards. Both water and wastewater treatment processes have necessarily become more advanced and complicated. Automation can reliably provide the critical, sophisticated control required to maintain adequate treatment. In his pollution abatement or water quality program, the environmental engineer can employ automatic control systems to continuously and accurately monitor contaminant levels or the removal efficiencies of treatment processes and to effect rapid responses when treatment adjustment becomes necessary by automatically adjusting processes

A Bio-Inspired Two-Layer Mixed-Signal Flexible Programmable Chip for Early Vision

A bio-inspired model for an analog programmable array processor (APAP), based on studies on the vertebrate retina, has permitted the realization of complex programmable spatio-temporal dynamics in VLSI. This model mimics the way in which images are processed in the visual pathway, what renders a feasible alternative for the implementation of early vision tasks in standard technologies. A prototype chip has been designed and fabricated in 0.5 μm CMOS. It renders a computing power per silicon area and power consumption that is amongst the highest reported for a single chip. The details of the bio-inspired network model, the analog building block design challenges and trade-offs and some functional tests results are presented in this paper.Office of Naval Research (USA) N-000140210884European Commission IST-1999-19007Ministerio de Ciencia y Tecnología TIC1999-082

ACE16K: The Third Generation of Mixed-Signal SIMD-CNN ACE Chips Toward VSoCs

Today, with 0.18-μm technologies mature and stable enough for mixed-signal design with a large variety of CMOS compatible optical sensors available and with 0.09-μm technologies knocking at the door of designers, we can face the design of integrated systems, instead of just integrated circuits. In fact, significant progress has been made in the last few years toward the realization of vision systems on chips (VSoCs). Such VSoCs are eventually targeted to integrate within a semiconductor substrate the functions of optical sensing, image processing in space and time, high-level processing, and the control of actuators. The consecutive generations of ACE chips define a roadmap toward flexible VSoCs. These chips consist of arrays of mixed-signal processing elements (PEs) which operate in accordance with single instruction multiple data (SIMD) computing architectures and exhibit the functional features of CNN Universal Machines. They have been conceived to cover the early stages of the visual processing path in a fully-parallel manner, and hence more efficiently than DSP-based systems. Across the different generations, different improvements and modifications have been made looking to converge with the newest discoveries of neurobiologists regarding the behavior of natural retinas. This paper presents considerations pertaining to the design of a member of the third generation of ACE chips, namely to the so-called ACE16k chip. This chip, designed in a 0.35-μm standard CMOS technology, contains about 3.75 million transistors and exhibits peak computing figures of 330 GOPS, 3.6 GOPS/mm2 and 82.5 GOPS/W. Each PE in the array contains a reconfigurable computing kernel capable of calculating linear convolutions on 3×3 neighborhoods in less than 1.5 μs, imagewise Boolean combinations in less than 200 ns, imagewise arithmetic operations in about 5 μs, and CNN-like temporal evolutions with a time constant of about 0.5 μs. Unfortunately, the many ideas underlying the design of this chip cannot be covered in a single paper; hence, this paper is focused on, first, placing the ACE16k in the ACE chip roadmap and, then, discussing the most significant modifications of ACE16K versus its predecessors in the family.LOCUST IST2001—38 097VISTA TIC2003—09 817 - C02—01Office of Naval Research N000 140 210 88