A digital tuning scheme for digitally programmable integrated continuous-time filters and techniques for high-precision monolithic linear circuit design and implementation

Multiple topics which all focus on precision monolithic circuit design but beyond this are not directly related to each other are presented. The first topic is a digital tuning scheme for digitally programmable integrated continuous-time filters (4), (8) - (10). Emphasis of this research is on development of a more general tuning scheme which can be applicable to various filter functions as well as high-frequency applications. The tuning scheme consists of two phases: system identification and adjustment. Various continuous-time filter identification methods including time-domain and frequency-domain approaches are investigated, and a filter adjustment algorithm is presented. Potential of high accuracy of the proposed tuning scheme and successful applicability to high-frequency filters with versatile functions have been demonstrated through simulations and experiments;Four other topics are separately presented. First, nonidealities associated with high-precision amplifiers (5), (7) are discussed. Special emphasis is given on analysis of statistical characteristics of random CMRR and offset of CMOS op-amps which can help estimating yield of high-volume production and help engineers design for a given yield. Next, an automatic offset compensation scheme for CMOS op-amps with ping-pong control (2), (6) is presented. A very low-voltage circuit design technique using floating gate MOSFETs (3) is introduced. Finally, an accurate and matching-free threshold voltage extraction scheme using a ratio-independent SC amplifier and a dynamic current mirror (1) is discussed

Solid State Circuits Technologies

The evolution of solid-state circuit technology has a long history within a relatively short period of time. This technology has lead to the modern information society that connects us and tools, a large market, and many types of products and applications. The solid-state circuit technology continuously evolves via breakthroughs and improvements every year. This book is devoted to review and present novel approaches for some of the main issues involved in this exciting and vigorous technology. The book is composed of 22 chapters, written by authors coming from 30 different institutions located in 12 different countries throughout the Americas, Asia and Europe. Thus, reflecting the wide international contribution to the book. The broad range of subjects presented in the book offers a general overview of the main issues in modern solid-state circuit technology. Furthermore, the book offers an in depth analysis on specific subjects for specialists. We believe the book is of great scientific and educational value for many readers. I am profoundly indebted to the support provided by all of those involved in the work. First and foremost I would like to acknowledge and thank the authors who worked hard and generously agreed to share their results and knowledge. Second I would like to express my gratitude to the Intech team that invited me to edit the book and give me their full support and a fruitful experience while working together to combine this book

New Mosfet Threshold Voltage Extraction Methods And Extractors

Tez (Yüksek Lisans) -- İstanbul Teknik Üniversitesi, Fen Bilimleri Enstitüsü, 2006Thesis (M.Sc.) -- İstanbul Technical University, Institute of Science and Technology, 2006MOSFET modellenmesinde çok önemli bir yer taşıyan eşik gerilimi, yapılan bir çok deneme sonucu matematiksel olarak hesaplanabilirken aynı zamanda çıkışında direk VTH’i veren basit devre yapıları ile de elde edilebilir. Bu çalışmada, kuvvetli-evirtim, lineer bölge, karakteristiklerine dayalı yeni eşik gerilimi elde etme yöntemleri önerilmiştir ve bu yöntemlere dayanarak çıkışlarında NMOS ve PMOS transistörler için eşik gerilimi veren devre yapılarının tasarımı anlatılmıştır. Önerlen yöntem temelde, analog bir yapı ile gerçeklenen aritmetik işlemin sonucuna dayandırılmıştır. Aritmetik işlem basit ve genelleştirilmiş olmak üzere iki yoldan incelenmiş ve bu yollardan her biri için üç farklı metod (IDPC,ICPD ve Esnek) önerilmiştir. Tasarlanan devrelerdeki mobilite etkisi, kanal boyu modülasyonu, boyut uyuşmazlığı ve gövde etkisi gibi ikinci dereceden etkiler analiz edilmiştir. Önerien devrelerde OPAMP, transistörleri linear bölgede kutuplamak, DDA ise çıkışında VTH’ı verecek olan aritmetik işlemi gerçeklemek için kullanılan yardımcı elemanlardır. Cadence-SpectreS ile yapılan ölçümler MOS transistörlerin eşik geriliminin tasarlanan yeni devreler ile % 1 veya % 0.8 hata ile elde edilebildiğini göstermiştir. NMOS eşik geriliminin sıcaklıkla negatif, PMOS eşik geriliminin sıcaklıkla pozitif olarak değişmesinden yararlanarak, sıcaklık katsayıları sırasıyla 1.9ْ9mV/Centigrade ve -1.42mV/Centigrade olan PTAT ve CTAT sıcaklık sensörler tasarlanmıştır. Yine aynı özellik yardımıyla OPAMP toplayıcı kullanılarak sıcaklık ve besleme gerilimi değişimlerinden bağımsız bir gerilim referans devresi elde edilmiştir.The threshold voltage value, which is the most important electrical parameter in modeling MOSFETs, can be extracted either from simulations or from the use of practical circuits which automatically and quickly yield the threshold voltage. In this thesis, new threshold voltage extraction methods based on the strong-inversion characteristic are proposed and the development of the NMOS and PMOS threshold voltage extractors implementing new methods is described. Proposed extraction method is based on an arithmetic operation which is classified into basic and generalized arithmetic operation schemes. Different implementations for each operation scheme such as IDPC, ICPD and Flexible method have been discussed and the effect of nonidealities such as mobility reduction, channel-length modulation, mismatch, and body effect has been analyzed. Auxiliary components are needed to perform design conditions. DDA operates as an arithmetic processor to precisely implement multiplication by two and subtraction as needed for extrapolation. OPAMP is also used to bias transistors in the linear region. The Cadence-SpectreS simulations confirm that threshold voltage of a MOS transistor can be extracted automatically using the VTH extractor without any need of calculation and delay. Additional applications such as temperature measurement, where the VTH extractor can be used either as a PTAT sensor or as a CTAT with small values of temperature coefficients (1.99mV/Centigrade and-1.42mV/Cent., respectively), and voltage reference circuit which is independent of temperature and supply voltage fluctuations, are presented.Yüksek LisansM.Sc

Statistical modelling of nano CMOS transistors with surface potential compact model PSP

The development of a statistical compact model strategy for nano-scale CMOS transistors is presented in this thesis. Statistical variability which arises from the discreteness of charge and granularity of matter plays an important role in scaling of nano CMOS transistors especially in sub 50nm technology nodes. In order to achieve reasonable performance and yield in contemporary CMOS designs, the statistical variability that affects the circuit/system performance and yield must be accurately represented by the industry standard compact models. As a starting point, predictive 3D simulation of an ensemble of 1000 microscopically different 35nm gate length transistors is carried out to characterize the impact of statistical variability on the device characteristics. PSP, an advanced surface potential compact model that is selected as the next generation industry standard compact model, is targeted in this study. There are two challenges in development of a statistical compact model strategy. The first challenge is related to the selection of a small subset of statistical compact model parameters from the large number of compact model parameters. We propose a strategy to select 7 parameters from PSP to capture the impact of statistical variability on current-voltage characteristics. These 7 parameters are used in statistical parameter extraction with an average RMS error of less than 2.5% crossing the whole operation region of the simulated transistors. Moreover, the accuracy of statistical compact model extraction strategy in reproducing the MOSFET electrical figures of merit is studied in detail. The results of the statistical compact model extraction are used for statistical circuit simulation of a CMOS inverter under different input-output conditions and different number of statistical parameters. The second challenge in the development of statistical compact model strategy is associated with statistical generation of parameters preserving the distribution and correlation of the directly extracted parameters. By using advanced statistical methods such as principal component analysis and nonlinear power method, the accuracy of parameter generation is evaluated and compared to directly extracted parameter sets. Finally, an extension of the PSP statistical compact model strategy to different channel width/length devices is presented. The statistical trends of parameters and figures of merit versus channel width/length are characterized

Current-Mode Techniques for the Implementation of Continuous- and Discrete-Time Cellular Neural Networks

This paper presents a unified, comprehensive approach to the design of continuous-time (CT) and discrete-time (DT) cellular neural networks (CNN) using CMOS current-mode analog techniques. The net input signals are currents instead of voltages as presented in previous approaches, thus avoiding the need for current-to-voltage dedicated interfaces in image processing tasks with photosensor devices. Outputs may be either currents or voltages. Cell design relies on exploitation of current mirror properties for the efficient implementation of both linear and nonlinear analog operators. These cells are simpler and easier to design than those found in previously reported CT and DT-CNN devices. Basic design issues are covered, together with discussions on the influence of nonidealities and advanced circuit design issues as well as design for manufacturability considerations associated with statistical analysis. Three prototypes have been designed for l.6-pm n-well CMOS technologies. One is discrete-time and can be reconfigured via local logic for noise removal, feature extraction (borders and edges), shadow detection, hole filling, and connected component detection (CCD) on a rectangular grid with unity neighborhood radius. The other two prototypes are continuous-time and fixed template: one for CCD and other for noise removal. Experimental results are given illustrating performance of these prototypes

Modeling and design of matching-critical circuits

Existing approaches for modeling mismatch effects in matching-critical circuits are based upon models derived under the widely accepted premise that distributed parameter devices can be modeled with lumped parameter models. It is shown in this dissertation that the lumped parameter models do not consistently reflect device performance and introduce substantial errors in matching-critical circuits if either systematic or random parameter variations occur in the channel. A new approach for characterizing the effects of both systematic and random variations in semiconductor device properties on device matching is introduced. This approach circumvents the introduction of model errors inherent in the existing approaches. A CAD tool, MOSGRAD, was developed to simulate the effects of distributed two-dimensional systematic and random variations in device parameters on the performance of matching-critical circuits. The tool is capable of predicting the performance of non-conventional circuit structures in which multiple drain and/or source regions that may or may not be rectangular and/or multiply segmented. Through the use of the tool, new current mirror layout strategies have been developed that exhibit reduced sensitivity to matching in the presence of linear parameter gradients

Impact of atomistic device variability on analogue circuit design

Scaling of complementary metal-oxide-semiconductor (CMOS) technology has benefited the semiconductor industry for almost half a century. For CMOS devices with a physical gate-length in the sub-100 nm range, extreme device variability is introduced and has become a major stumbling block for next generation analogue circuit design. Both opportunities and challenges have therefore confronted analogue circuit designers. Small geometry device can enable high-speed analogue circuit designs, such as data conversion interfaces that can work in the radio frequency range. These designs can be co-integrated with digital systems to achieve low cost, high-performance, single-chip solutions that could only be achieved using multi-chip solutions in the past. However, analogue circuit designs are extremely vulnerable to device mismatch, since a large number of symmetric transistor pairs and circuit cells are required. The increase in device variability from sub-100 nm processes has therefore significantly reduced the production yield of the conventional designs. Mismatch models have been developed to analytically evaluate the magnitude of random variations. Based on measurements from custom designed test structures, the statistics of process variation can be estimated using design related parameters. However, existing models can no longer accurately estimate the magnitude of mismatch for sub-100 nm “atomistic” devices, since short-channel effects have become important. In this thesis, a new mismatch model for small geometry devices will be proposed to address this problem. Based on knowledge of the matching performance obtained from the mismatch model, design solutions are desired at different design levels for a variety of circuit topologies. In this thesis, transistor level compensation solutions have been investigated and closed-loop compensation circuits have been proposed. At circuit level, a latch-based comparator has been used to develop a compensation solution because this type of comparator is extremely sensitive to the device mismatch. These comparators are also used as the fundamental building block for the analogue-to-digital converters (ADC). The proposed comparator compensation scheme is used to improve the performance of a high-speed flash ADC

High Efficiency IGBTs through Novel Three-Dimensional Modelling and New Architectures

New Insulated Gate Bipolar Transistor (IGBT) designs are reliant on simulation tools, such as Sentaurus technology computer-aided design (TCAD) models, which allow for rapid device development that could not be achieved by manufacturing prototypes due to the cost and time associated with fabrication. These simulations are, though, computationally expensive and typically most design engineers develop these TCAD models only in two dimensions. This leads to inaccuracies in the model output since manufactured transistors are inherently three-dimensional (3D). Based upon a commercial IGBT, this thesis begins by outlining the development of a 3D TCAD model using design details provided by the manufacturer. Large variations between the experimental data from the manufactured device and the simulation model lead to the discovery of widespread birds-beaking within the IGBT – an uncontrollable processing defect that the manufacturer was unaware of. This thesis presents a new simulation technique to account for this processing error while minimising computational effort and investigates the consequence of this birds-beak on the reliability of the device. The verified 3D IGBT model was also used to determine an optimum cell design that considered critical 3D effects omitted from previous studies. An extensive literature review for the Reverse-Conducting IGBT (RC-IGBT) is provided. It is shown that despite the benefits of the RC-IGBT, the device suffers from many undesirable design trade-offs that have prevented its widespread use. The RC-IGBT designs that have currently been proposed in literature, either present a trade-off in performance, an inability to be manufactured, or a requirement for a custom gate drive. This thesis presents a new RC-IGBT concept, the ‘Dual Implant SuperJunction (SJ) RC-IGBT’ that addresses these concerns and is manufacturable using current state of the art techniques. The concept and proposed manufacturing method enables, for the first time, a full SuperJunction structure to be achieved in a 1.2kV device. In addition, an investigation into a coordinated switching scheme using both a silicon IGBT and silicon-carbide MOSFET was undertaken, which aimed to improve turn-off losses within the IGBT without sacrificing on-state losses. Thermal modelling of the power devices switching under inductive load was explored as the system was optimised to use a SiC MOSFET in excess of its nominal ratings, reducing the overall system cost.EPSRC Doctoral Training Partnership scheme (grant RG75686