High-Speed Low-Power Analog to Digital Converter for Digital Beam Forming Systems

abstract: Time-interleaved analog to digital converters (ADCs) have become critical components in high-speed communication systems. Consumers demands for smaller size, more bandwidth and more features from their communication systems have driven the market to use modern complementary metal-oxide-semiconductor (CMOS) technologies with shorter channel-length transistors and hence a more compact design. Downscaling the supply voltage which is required in submicron technologies benefits digital circuits in terms of power and area. Designing accurate analog circuits, however becomes more challenging due to the less headroom. One way to overcome this problem is to use calibration to compensate for the loss of accuracy in analog circuits. Time-interleaving increases the effective data conversion rate in ADCs while keeping the circuit requirements the same. However, this technique needs special considerations as other design issues associated with using parallel identical channels emerge. The first and the most important is the practical issue of timing mismatch between channels, also called sample-time error, which can directly affect the performance of the ADC. Many techniques have been developed to tackle this issue both in analog and digital domains. Most of these techniques have high complexities especially when the number of channels exceeds 2 and some of them are only valid when input signal is a single tone sinusoidal which limits the application. This dissertation proposes a sample-time error calibration technique which bests the previous techniques in terms of simplicity, and also could be used with arbitrary input signals. A 12-bit 650 MSPS pipeline ADC with 1.5 GHz analog bandwidth for digital beam forming systems is designed in IBM 8HP BiCMOS 130 nm technology. A front-end sample-and-hold amplifier (SHA) was also designed to compare with an SHA-less design in terms of performance, power and area. Simulation results show that the proposed technique is able to improve the SNDR by 20 dB for a mismatch of 50% of the sampling period and up to 29 dB at 37% of the Nyquist frequency. The designed ADC consumes 122 mW in each channel and the clock generation circuit consumes 142 mW. The ADC achieves 68.4 dB SNDR for an input of 61 MHz.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

A 1.8V 12-bit 230-MS/s pipeline ADC in 0.18um CMOS technology

This paper describes the implementation of a 12-bit 230 MS/s pipelined ADC using a conventional 1.8V, 0.18μm digital CMOS process. Two-stage folded cascode OTA topology is used for improved settling performance. Extreme low-skew (less than 3ps peak-to-peak) chip-level clock distribution is ensured by five-level balanced clock tree, implemented in low swing current-mode logic. The ADC block achieves a peak SFDR of 71.3 dB and 9.26 ENOB at 230 MS/s, with an input signal swing of 1.5Vpp. The measured peak SFDR at 200 MS/s is 78 dB, while the peak SNDR at 200 MS/s is 59.5 dB. The SFDR and SNDR performance exhibits very flat characteristics, maintaining higher than 53 dB SNDR at 230 MS/s and higher than 58 dB SNDR at 200 MS/s, from DC through Nyquist rate input frequencies

Low-power high-speed ADC design techniques in scaled CMOS process

The power consumption of a single-channel successive approximation register (SAR) analog-to-digital (ADC) tends to linearly increase with its sampling rate (f[subscript s]), when f[subscript s] is small. However, when f[subscript s] passes a certain point for a given technology node, the ADC power P increases at much higher rate and the normalized power efficiency (P/f[subscript s]) starts to degrade rapidly. To enhance the conversion speed of SAR ADC, while maintaining a good power efficiency, this thesis presents speed-enhancing techniques for SAR ADC in nano-scale CMOS technologies. First chapter presents a 2b/cycle hybrid SAR architecture with only 1 differential capacitor-DAC (CDAC). Unlike prior multi-bit/cycle SAR works that make use of only the DAC differential mode (DM) voltage, the proposed architecture exploits both the DM and the common mode (CM). By using two degrees of freedom, 2b/cycle conversion technique can boost the f[subscript s] of the ADC without any additional DAC arrays. High-speed ADCs can boost the conversion speed not only by increasing the f[subscript s] of a single-channel ADC, but also by time-interleaving multiple ADC sub-channels running at a lower rate. For an N-channel time-interleaved (TI) SAR ADC operating at f[subscript s], each sub-SAR channel only needs to operate at f[subscript s]=N. Therefore, each sub-SAR can operate in the linear power versus speed region, leading to a significant power saving compared to a single-channel ADC running at the same sampling rate. Despite of its power efficiency, TI-ADC suffers from mismatches among sub-ADC channels, including gain, offset, and timing mismatches. Among them, timing skew is one of the most difficult errors to calibrate as it is nontrivial to extract and its induced error depends on both the frequency and the amplitude of the input signal. Second chapter of this thesis presents a TI-SAR with a fast variance-based timing-skew calibration technique. It uses a single-comparator based window detector (WD) to calibrate the timing skew. The WD suppresses variance estimation errors and allow precise variance estimation from a significantly small number of samples. It has low-hardware cost and orders of magnitude faster convergence speed compared to prior variance-based timing-skew calibration technique. The last chapter presents another TI-SAR with mean absolute deviation (MAD) based timing-skew calibration technique. In addition to all the advantages presented with the fast variance-based timing-skew calibration technique, the proposed technique further reduces the digital computation power by 50% by eliminating the squaring operations, which are essential in variance-based calibration techniqueElectrical and Computer Engineerin

High-Speed Pipeline Analog-to-Digital Converter: Transistor-Level Design and Calibration Issues

La tesi riguarda la progettazione dei blocchi essenziali di un convertitore pipeline ad alta velocità (250MHz) a capacità commutate. Il lavoro inoltre include uno studio approfondito su due possibili tecniche di calibrazione del guadagno, delle non-linearità e del mismatch capacitivo

Digitally Assisted Multi-Channel Receivers

This work presents a data estimation scheme for wide band multi-channel charge sampling receivers with sinc filter banks together with a complete system calibration and synchronization algorithm for the receiver. A unified model has been defined for the receiver containing all first order mismatches, offsets and imperfections and a technique based on least mean squares algorithm is employed to track these errors. The performance of this technique under noisy channel conditions has been verified. The sinc filter bank is compared with the conventional analog filter banks and it is shown that the sinc filter banks have very low computational complexity in data estimation Nextly, analytical tools for the design of clock-jitter tolerant multi-channel filterbank receivers have been developed. Clock-jitter is one of the most fundamental obstacles for the future generation of wideband receivers. Additionally all the trade-offs and specifications of a design example for a multi-channel receiver that can process a 5 GHz baseband signal with 40 dB of signal-to-noise-ratio (SNR) using sampling clocks that can tolerate up to 5 ps of clock-jitter standard deviation are presented. A novel bandwidth optimization technique has been presented. As a part of it the bandwidth of the filters present in each path is optimized thereby improving the performance of the receiver further in the presence of sampling clock jitter. The amount of bandwidth reduction possible depends on the order of the filter and the noise amplification provided by the reconstruction matrix. It has been shown that 3rd order filters of bandwidth 1 GHz can be replaced with 1st order filters of bandwidth 100 MHz without any depreciation in the output resolution, implying huge power savings

Digitally-Assisted Mixed-Signal Wideband Compressive Sensing

Digitizing wideband signals requires very demanding analog-to-digital conversion (ADC) speed and resolution specifications. In this dissertation, a mixed-signal parallel compressive sensing system is proposed to realize the sensing of wideband sparse signals at sub-Nqyuist rate by exploiting the signal sparsity. The mixed-signal compressive sensing is realized with a parallel segmented compressive sensing (PSCS) front-end, which not only can filter out the harmonic spurs that leak from the local random generator, but also provides a tradeoff between the sampling rate and the system complexity such that a practical hardware implementation is possible. Moreover, the signal randomization in the system is able to spread the spurious energy due to ADC nonlinearity along the signal bandwidth rather than concentrate on a few frequencies as it is the case for a conventional ADC. This important new property relaxes the ADC SFDR requirement when sensing frequency-domain sparse signals. The mixed-signal compressive sensing system performance is greatly impacted by the accuracy of analog circuit components, especially with the scaling of CMOS technology. In this dissertation, the effect of the circuit imperfection in the mixed-signal compressive sensing system based on the PSCS front-end is investigated in detail, such as the finite settling time, the timing uncertainty and so on. An iterative background calibration algorithm based on LMS (Least Mean Square) is proposed, which is shown to be able to effectively calibrate the error due to the circuit nonideal factors. A low-speed prototype built with off-the-shelf components is presented. The prototype is able to sense sparse analog signals with up to 4 percent sparsity at 32 percent of the Nqyuist rate. Many practical constraints that arose during building the prototype such as circuit nonidealities are addressed in detail, which provides good insights for a future high-frequency integrated circuit implementation. Based on that, a high-frequency sub-Nyquist rate receiver exploiting the parallel compressive sensing is designed and fabricated with IBM90nm CMOS technology, and measurement results are presented to show the capability of wideband compressive sensing at sub-Nyquist rate. To the best of our knowledge, this prototype is the first reported integrated chip for wideband mixed-signal compressive sensing. The proposed prototype achieves 7 bits ENOB and 3 GS/s equivalent sampling rate in simulation assuming a 0.5 ps state-of-art jitter variance, whose FOM beats the FOM of the high speed state-of-the-art Nyquist ADCs by 2-3 times. The proposed mixed-signal compressive sensing system can be applied in various fields. In particular, its applications for wideband spectrum sensing for cognitive radios and spectrum analysis in RF tests are discussed in this work

Improving Accuracy and Energy Efficiency of Pipeline Analog to Digital Converters

Analog-to-Digital converters (ADC) are key building blocks of analog and mixed-signal processing that link the natural world of analog signals and the world of digital processing. This work describes the analysis, design, development and test of novel high-resolution (≥12-bit), moderate speed (10-100MS/s), energy-efficient ADCs. Such ADCs are typically used for communication, imaging and video applications. CMOS process scaling is typically aimed at enabling fast, low-power digital circuits. Scaling leads to lower supply voltages, and to short channel devices with low gain and poor matching between small devices. On the other hand, to process and amplify analog signals analog circuits rely on wide signal swing, large transistor gain and good component matching. Hence, analog circuit performance has lagged far behind digital performance. Analog circuits such as ADCs are therefore nowadays performance bottlenecks in many electronic systems. The pipeline ADC is a popular architecture for implementing ADCs with a wide range of speed and resolution. This work aims to improve the accuracy and energy efficiency of the pipeline architecture by combining it with more accurate or more energy efficient architectures such as Sigma-Delta and Successive-Approximation (SAR). Such novel, hybrid architectures are investigated in this work. In the first design, a new architecture is developed which combines a low-OSR resetting Sigma-Delta modulator architecture with the pipeline architecture. This architecture enhances the accuracy and energy efficiency of the pipeline architecture. A prototype 14-bit 23MS/s ADC, based on this new architecture, is designed and tested. This ADC achieves calibration-free 14-bit linearity, 11.7-bit ENOB and 87dB SFDR while dissipating only 48mW of power. In the second design, new hybrid architecture based on SAR and pipeline architecture is developed. This architecture significantly improves the energy efficiency of the pipeline architecture. A prototype 12-bit 50MS/s ADC is designed based on this new architecture. “Half-gain” and “half-reference” pipeline stages are also introduced in this prototype for the first time to further reduce power dissipation. This ADC dissipates only 3.5mW power.Ph.D.Electrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/76025/1/leechun_1.pd

Design and debugging of multi-step analog to digital converters

With the fast advancement of CMOS fabrication technology, more and more signal-processing functions are implemented in the digital domain for a lower cost, lower power consumption, higher yield, and higher re-configurability. The trend of increasing integration level for integrated circuits has forced the A/D converter interface to reside on the same silicon in complex mixed-signal ICs containing mostly digital blocks for DSP and control. However, specifications of the converters in various applications emphasize high dynamic range and low spurious spectral performance. It is nontrivial to achieve this level of linearity in a monolithic environment where post-fabrication component trimming or calibration is cumbersome to implement for certain applications or/and for cost and manufacturability reasons. Additionally, as CMOS integrated circuits are accomplishing unprecedented integration levels, potential problems associated with device scaling – the short-channel effects – are also looming large as technology strides into the deep-submicron regime. The A/D conversion process involves sampling the applied analog input signal and quantizing it to its digital representation by comparing it to reference voltages before further signal processing in subsequent digital systems. Depending on how these functions are combined, different A/D converter architectures can be implemented with different requirements on each function. Practical realizations show the trend that to a first order, converter power is directly proportional to sampling rate. However, power dissipation required becomes nonlinear as the speed capabilities of a process technology are pushed to the limit. Pipeline and two-step/multi-step converters tend to be the most efficient at achieving a given resolution and sampling rate specification. This thesis is in a sense unique work as it covers the whole spectrum of design, test, debugging and calibration of multi-step A/D converters; it incorporates development of circuit techniques and algorithms to enhance the resolution and attainable sample rate of an A/D converter and to enhance testing and debugging potential to detect errors dynamically, to isolate and confine faults, and to recover and compensate for the errors continuously. The power proficiency for high resolution of multi-step converter by combining parallelism and calibration and exploiting low-voltage circuit techniques is demonstrated with a 1.8 V, 12-bit, 80 MS/s, 100 mW analog to-digital converter fabricated in five-metal layers 0.18-µm CMOS process. Lower power supply voltages significantly reduce noise margins and increase variations in process, device and design parameters. Consequently, it is steadily more difficult to control the fabrication process precisely enough to maintain uniformity. Microscopic particles present in the manufacturing environment and slight variations in the parameters of manufacturing steps can all lead to the geometrical and electrical properties of an IC to deviate from those generated at the end of the design process. Those defects can cause various types of malfunctioning, depending on the IC topology and the nature of the defect. To relive the burden placed on IC design and manufacturing originated with ever-increasing costs associated with testing and debugging of complex mixed-signal electronic systems, several circuit techniques and algorithms are developed and incorporated in proposed ATPG, DfT and BIST methodologies. Process variation cannot be solved by improving manufacturing tolerances; variability must be reduced by new device technology or managed by design in order for scaling to continue. Similarly, within-die performance variation also imposes new challenges for test methods. With the use of dedicated sensors, which exploit knowledge of the circuit structure and the specific defect mechanisms, the method described in this thesis facilitates early and fast identification of excessive process parameter variation effects. The expectation-maximization algorithm makes the estimation problem more tractable and also yields good estimates of the parameters for small sample sizes. To allow the test guidance with the information obtained through monitoring process variations implemented adjusted support vector machine classifier simultaneously minimize the empirical classification error and maximize the geometric margin. On a positive note, the use of digital enhancing calibration techniques reduces the need for expensive technologies with special fabrication steps. Indeed, the extra cost of digital processing is normally affordable as the use of submicron mixed signal technologies allows for efficient usage of silicon area even for relatively complex algorithms. Employed adaptive filtering algorithm for error estimation offers the small number of operations per iteration and does not require correlation function calculation nor matrix inversions. The presented foreground calibration algorithm does not need any dedicated test signal and does not require a part of the conversion time. It works continuously and with every signal applied to the A/D converter. The feasibility of the method for on-line and off-line debugging and calibration has been verified by experimental measurements from the silicon prototype fabricated in standard single poly, six metal 0.09-µm CMOS process

Design of Inverter Based CMOS Amplifiers in Deep Nanoscale Technologies

In this work, it is proposed a fully differential ring amplifier topology with a deadzone voltage created by a CMOS resistor with a biasing circuit to increase the robustness over PVT variations. The study focuses on analyzing the performance of the ring amplifier over process, temperature, and supply voltage variations, in order to guarantee a viable industrial employment in a 7 nm FinFET CMOS technology node for being used as residue amplifier in ADCs. A ring amplifier is a small modular amplifier, derived from a ring oscillator. It is simple enough that it can quickly be designed using only a few inverters, capacitors, and switches. It can amplify with rail-to-rail output swing, competently charge large capacitive loads using slew-based charging, and scale well in performance according to process trends. In typical process corner, a gain of 72 dB is achieved with a settling time of 150 ps. Throughout the study, the proposed topology is compared with others presented in literature showing better results over corners and presenting a faster response. The proposed topology isn’t yet suitable for industry use, because it presents one corner significantly slower than the rest, namely process corner FF 125 °C, and process corner FS -40 °C with a small oscillation throughout the entire amplification period. Nevertheless, it proved itself to be a promising technique, showing a high gain and a fast settling without oscillation phase, with room for improvement.Neste trabalho, é proposta uma topologia de ring amplifier com a deadzone a ser criada através de uma resistência CMOS com um circuito de polarização para aumentar a robustez para as variações PVT. O estudo foca-se em analisar a performance do ring amplifier nas variações de processo, temperatura e tensão de alimentação, de forma a garantir um uso viável em indústria na tecnologia de 7 nm FinFET CMOS, para ser usado como amplificador de resíduo em ADCs. Um ring amplifier é um pequeno amplificador modular, derivado do ring oscillator. É simples o suficiente para ser facilmente projetado usando apenas poucos inversores, condensadores e interruptores. Consegue amplificar com rail-to-rail output swing, carregar grandes cargas capacitivas com carregamento slew-based e escalar bem em termos de performance de acordo com o processo. No typical process corner, foi obtido um ganho de 72 dB com um tempo de estabilização de 150 ps. Durante o estudo, a topologia proposta é comparada com outras presentes na literatura mostrando melhores resultados over corners e apresentando uma resposta mais rápida. A topologia proposta ainda não está preparada para uso industrial uma vez que apresenta um corner significativamente mais lento que os restantes, nomeadamente, process corner FF 125 °C, e outro process corner, FS -40 °C, com uma pequena oscilação durante todo o período de amplificação. Todavia, provou ser uma técnica promissora, apresentando um ganho elevado e uma rápida estabilização sem fase de oscilação, com espaço para melhoria

A comparative study between sinusoidal and squarewave clocking for alleviating the jitter limitation in multi-gigaHertz ADCs

Various applications like wireless UWB communication, fast data acquisition systems and digital storage oscilloscopes needs ADCs with instantaneous input signal bandwidth from 0.1-40 GigaHertz range with 6-10 bits of resolution -- a challenging task and an impressive goal to achieve. Flash ADCs have been conventionally employed to achieve these goals but have been proved to be power hungry and ineffective for higher resolution. Time-interleaved converters are another option that relax the device speed and circuit complexity. Current research shows that at high input frequencies in the MultiGigaHertz range, the performance of these time-interleaved high speed ADCs is limited mainly by the sampling clock jitter. In this work, the effect of clock jitter on the data acquisition for a sampled data system is analyzed and discussed. Under the premise that, for a given jitter specification, it is relatively easy to generate a clean high frequency sinusoidal signal than a high frequency squarewave signal, this proposed work makes use of a clean sinusoid as the sampling clock. This high frequency sinusoidal clock, embedded with low frequency squarewave clocks, is employed in a proposed bottom plate sampling Track-and-Hold (T/H) architecture with the aim of improving the SNR at multi-GigaHertz frequencies. A comparative study on the performance of this T/H circuit (SNDR,ENOB) for sinusoidal sampling and conventional squarewave sampling is presented. The work concludes that for high frequency sampled data acquisition system, where sampling clock with sub-1ps jitter values are needed, the presented scheme of sinusoidal sampling is advantageous for reducing sampling clock uncertainty when compared against the conventional squarewave sampling technique