Optimized fractional-order Butterworth filter design in complex F-plane

This paper introduces a new technique to optimally design the fractional-order Butterworth low-pass filter in the complex F-plane. Design stability is assured by incorporating the critical phase angle as an inequality constraint. The poles of the proposed approximants reside on the unit circle in the stable region of the F-plane. The improved accuracy of the suggested scheme as compared to the recently published literature is demonstrated. A mixed-integer genetic algorithm which considers the parallel combinations of resistors and capacitors for the Valsa network is used to optimize the frequency responses of the fractional-order capacitor emulators as part of the experimental verification using the Sallen–Key filter topology. The total harmonic distortion and spurious-free dynamic range of the practical 1.5th-order Butterwoth filter are measured as 0.13% and 62.18 dBc, respectively; the maximum and mean absolute relative magnitude errors are 0.03929 and 0.02051, respectively.Publisher's VersionQ1WOS:00085474580000

Switched capacitor networks : a novel prewarping procedure

Bibliography: leaves 152-157.Novel methods for prewarping filter specifications prior to realization. in Switched Capacitor (SC) form are presented. These allow the design of arbitrary response requirements, exhibiting a low amount of error that normally results from the frequency warping associated with sampled-data networks. Adjustment is applied to the pole and zero locations of a reference filter, using three distinct approaches (Center frequency "CF", Selectivity "S" and Complex Mapping "CM" pole/zero prewarping), developed for both the Lossless Discrete Integrator (LOI) and Bilinear (Bil) analog to digital transformations. The derivation of the prewarping expressions is explained with reference to these mappings, and the effect they have on the apparent pole and zero locations of an SC filter realization

Architectural Improvements Towards an Efficient 16-18 Bit 100-200 MSPS ADC

As Data conversion systems continue to improve in speed and resolution, increasing demands are placed on the performance of high-speed Analog to Digital Conversion systems. This work makes a survey about all these and proposes a suitable architecture in order to achieve the desired specifications of 100-200MS/s with 16-18 bit of resolution. The main architecture is based on paralleled structures in order to achieve high sampling rate and at the same time high resolution. In order to solve problems related to Time-interleaved architectures, an advanced randomization method was introduced. It combines randomization and spectral shaping of mismatches. With a simple low-pass filter the method can, compared to conventional randomization algorithms, improve the SFDR as well as the SINAD. The main advantage of this technique over previous ones is that, because the algorithm only need that ADCs are ordered basing on their time mismatches, the absolute accuracy of the mismatch identification method does not matter and, therefore, the requirements on the timing mismatch identification are very low. In addition to that, this correction system uses very simple algorithms able to correct not only for time but also for gain and offset mismatches

Extending the calibration in the Underwater Sound Reference Division (USRD) reciprocity coupler to incorporate phase

In this report, a phase measurement is added to the Underwater Sound Reference Division (USRD) reciprocity coupler primary calibration procedure for an H48 reference hydrophone. Data acquisition equipment is added to record time-series data from the hydrophone under test and from the reciprocal transducers. The complex-valued hydrophone sensitivity is calculated. The sensitivity magnitude is compared to measurements from the standard coupler calibration procedure, and the complex sensitivity data are also fitted to a simple high-pass circuit model. The model is used to estimate the low-frequency cutoff of H48 hydrophone SN4. The low-frequency cutoff measured in this report is about 0.2 Hz higher than that originally measured and specified when the H48 hydrophones were first built. The new results show significant roll-off in phase below 10-20 Hz, a range where the phase is typically assumed flat during the standard calibration. By 1 Hz the phase roll-off is about 20°. The error analysis of the original coupler is summarized and error and uncertainty due to new data acquisition equipment and phase measurement added. Some errors due to simplifications in the acoustics of the coupler are left to future work.http://archive.org/details/extendingcalibra1094550486Civilian, Department of the NavyApproved for public release; distribution is unlimited

Process and Temperature Compensated Wideband Injection Locked Frequency Dividers and their Application to Low-Power 2.4-GHz Frequency Synthesizers

There has been a dramatic increase in wireless awareness among the user community in the past five years. The 2.4-GHz Industrial, Scientific and Medical (ISM) band is being used for a diverse range of applications due to the following reasons. It is the only unlicensed band approved worldwide and it offers more bandwidth and supports higher data rates compared to the 915-MHz ISM band. The power consumption of devices utilizing the 2.4-GHz band is much lower compared to the 5.2-GHz ISM band. Protocols like Bluetooth and Zigbee that utilize the 2.4-GHz ISM band are becoming extremely popular. Bluetooth is an economic wireless solution for short range connectivity between PC, cell phones, PDAs, Laptops etc. The Zigbee protocol is a wireless technology that was developed as an open global standard to address the unique needs of low-cost, lowpower, wireless sensor networks. Wireless sensor networks are becoming ubiquitous, especially after the recent terrorist activities. Sensors are employed in strategic locations for real-time environmental monitoring, where they collect and transmit data frequently to a nearby terminal. The devices operating in this band are usually compact and battery powered. To enhance battery life and avoid the cumbersome task of battery replacement, the devices used should consume extremely low power. Also, to meet the growing demands cost and sized has to be kept low which mandates fully monolithic implementation using low cost process. CMOS process is extremely attractive for such applications because of its low cost and the possibility to integrate baseband and high frequency circuits on the same chip. A fully integrated solution is attractive for low power consumption as it avoids the need for power hungry drivers for driving off-chip components. The transceiver is often the most power hungry block in a wireless communication system. The frequency divider (prescaler) and the voltage controlled oscillator in the transmitter’s frequency synthesizer are among the major sources of power consumption. There have been a number of publications in the past few decades on low-power high-performance VCOs. Therefore this work focuses on prescalers. A class of analog frequency dividers called as Injection-Locked Frequency Dividers (ILFD) was introduced in the recent past as low power frequency division. ILFDs can consume an order of magnitude lower power when compared to conventional flip-flop based dividers. However the range of operation frequency also knows as the locking range is limited. ILFDs can be classified as LC based and Ring based. Though LC based are insensitive to process and temperature variation, they cannot be used for the 2.4-GHz ISM band because of the large size of on-chip inductors at these frequencies. This causes a lot of valuable chip area to be wasted. Ring based ILFDs are compact and provide a low power solution but are extremely sensitive to process and temperature variations. Process and temperature variation can cause ring based ILFD to loose lock in the desired operating band. The goal of this work is to make the ring based ILFDs useful for practical applications. Techniques to extend the locking range of the ILFDs are discussed. A novel and simple compensation technique is devised to compensate the ILFD and keep the locking range tight with process and temperature variations. The proposed ILFD is used in a 2.4-GHz frequency synthesizer that is optimized for fractional-N synthesis. Measurement results supporting the theory are provided

Direct Digital Frequency Synthesizer Architecture for Wireless Communication in 90 NM CMOS Technology

Software radio is one promising field that can meet the demands for low cost, low power, and high speed electronic devices for wireless communication. At the heart of software radio is a programmable oscillator called a Direct Digital Synthesizer (DDS). DDS has the capabilities of rapid frequency hopping by digital software control while operating at very high frequencies and having sub-hertz resolution. Nevertheless, the digital-to-analog converter (DAC) and the read-only-memory (ROM) look-up table, building blocks of the DDS, prevent the DDS to be used in wireless communication because they introduce errors and noises to the DDS and their performances deteriorate at high speed. The DAC and ROM are replaced in this thesis by analog active filters that convert the square wave output of the phase accumulator directly into a sine wave. The proposed architecture operates with a reference clock of 9.09 GHz and can be fully-integrated in 90 nm CMOS technology