Transmissor RF de elevado rendimento com duas entradas digitais para sistemas 5G

In recent years, there has been a need to increase the capacity and speed of information transmission, so the communication signals used in mobile communications have been improved to meet the expectations. This will be even more significant in future 5G systems, since due to the high expansion of wireless devices, current 4G systems are starting to push their limits, where only small improvements can be achieved. Which complicates the design of transmitters, since these new signals have a wider bandwidth and a large variation between their average and peak value, causing amplifiers to operate most of the time in a zone where they are not as efficient. For this reason, amplifier architectures not only aim to have high efficiency when operating at maximum signal excursion, but also to increase efficiency in the zone where they will operate most of the time. For this purpose, there are architectures based on supply voltage modulation and load modulation to improve the efficiency at lower powers. This work addresses load modulation architectures, where Doherty and Chireix are the most prominent. In addition, with the increase in digital signal processing capabilities, new amplification architectures based on the load modulation technique have recently been proposed, but instead of using only one RF input, they use two independent digitally controlled inputs. This dissertation aims at implementing a Doherty-Chireix amplifier with two digital inputs to achieve efficient amplification for the 1.7 to 2.4GHz frequency band. In the end it was possible to design and implement a Doherty-Chireix power amplifier, with 700MHz bandwidth, with a gain between 13.9-11.3dB, a maximum power of 45dBm, a PAE of over 60% and peak-to-average power ratio between 5.2-4.1dB.Nos últimos anos, tem havido uma necessidade de aumentar a capacidade e velocidade de transmissão de informação, deste modo os sinais de comunicação utilizados nas comunicações móveis têm evoluído por forma a corresponder as expectativas. Tal será ainda mais significativo nos futuros sistemas 5G, já que devido à elevada expansão de dispositivos sem fio, os atuais sistemas 4G estão a começar a atingir os seus limites, onde apenas pequenas melhorias podem ser alcançadas. Isto vem complicar o projeto dos transmissores, uma vez que estes novos sinais apresentam uma maior largura de banda e uma grande variação entre o seu valor médio e de pico, fazendo com que os amplificadores operem na maior parte do tempo numa zona em que não são tão eficientes. Por esta razão, as arquiteturas de amplificação nos dias de hoje não só visam ter um grande rendimento quando operam com a máxima excursão de sinal, mas também o aumento do rendimento na zona onde irão operar a maior parte do tempo. Nesse sentido existem arquiteturas baseadas em modelação de tensão de alimentação e modelação de carga de modo a melhorar a eficiência a potências mais baixas. Neste trabalho são abordadas arquiteturas de modulação de carga, onde Doherty e Chireix são as que mais se destacam. Para além disso, com o aumento da capacidade de processamento digital de sinal, recentemente foram propostas novas arquiteturas de amplificação que se baseiam nestas técnicas, mas em vez de utilizar apenas uma entrada de RF, usam duas entradas independentes controladas digitalmente. Esta dissertação visa a implementação de um amplificador Doherty-Chireix com duas entras digitais de modo a obter uma amplificação eficiente para uma banda de frequências de 1.7 a 2.4GHz. No final foi possível projetar e implementar um amplificador de potência Doherty-Chireix, com 700MHz de largura de banda, com um ganho compreendido entre 13.9-11.3dB, potência máxima de 45dBm, uma PAE superior a 60% e peak-to-average power ratio entre 5.2-4.1dB.Mestrado em Engenharia Eletrónica e Telecomunicaçõe

A 39-GHz Doherty-Like Power Amplifier with 22-dBm Output Power and 21% Power-Added Efficiency at 6-dB Power Back-Off

© 2024, IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. This is the accepted manuscript version of a conference paper which has been published in final form at https://doi.org/10.1109/JETCAS.2024.3351075The design of a Doherty-like power amplifier for millimetre-wave (mm-wave) applications is presented in this work. The designed power amplifier employs a novel symmetrical loadmodulated balanced amplifier (S-LMBA) architecture. This design is advantageous in minimizing the undesired impedance interaction often encountered in the classic LMBA approach. Such interactions are typically due to the use of a non-50 Ω load at the isolation port of the output quadrature coupler. Moreover, magnitude and phase control networks are carefully designed to generate the specific magnitude and phase information for the designed S-LMBA. To demonstrate the proposed ideas, the SLMBA is fabricated in a 45-nm CMOS SOI technology. At 39 GHz, a 22.1 dBm saturated output power (Psat) with a maximum poweradded efficiency (PAE) of 25.7% is achieved. In addition, 1.68 times drain efficiency enhancement is obtained over an ideal Class-B operation, when the designed S-LMBA is operated at 6 dB power back-off. An average output power of 13.1 dBm with a PAE of 14.4% at an error vector magnitude (EVMrms) above -22.5 dB and adjacent channel power ratio (ACPR) of -23 dBc is also achieved, when a 200 MHz single carrier 64-quadratureamplitude- modulation (QAM) signal is used. Including all testing pads, the footprint of the designed S-LMBA is only 1.56 mm2.Peer reviewe

A review of technologies and design techniques of millimeter-wave power amplifiers

his article reviews the state-of-the-art millimeter-wave (mm-wave) power amplifiers (PAs), focusing on broadband design techniques. An overview of the main solid-state technologies is provided, including Si, gallium arsenide (GaAs), GaN, and other III-V materials, and both field-effect and bipolar transistors. The most popular broadband design techniques are introduced, before critically comparing through the most relevant design examples found in the scientific literature. Given the wide breadth of applications that are foreseen to exploit the mm-wave spectrum, this contribution will represent a valuable guide for designers who need a single reference before adventuring in the challenging task of the mm-wave PA design

Intrinsically Mode Reconfigurable Load Modulation Balanced Amplifier Leveraging Transistor\u27s Analog-Digital Duality

The communication schemes have rapidly changed the face of the human means of communication. The evolution from one generation to another has triggered many challenges on the design methodologies of RF designers. As the evolution ensued, the spectrally efficient modulation schemes have resulted in the substantial rise of PAPR, the peak-to-average power ratio. To enable the efficient amplification of the high PAPR signals, this thesis explores the areas of Load modulated Balanced amplifiers that can be inherently reconfigured to achieve a better efficiency than the conventional RF power amplifiers that see a significant drop in the efficiency as the signal is backed-off from the maximum power level. In the communication environment, the load mismatch to the power amplifier does result in the degraded efficiency profile which is detrimental to the performance of the communication system. Hence, the power amplifier stage needs to be mismatch resilient. A three mode reconfigurable balanced power amplifier that can tolerate the mismatch due to the antenna array in massive MIMO is presented. The transistor\u27s analog-digital duality is exploited for deploying it as an amplifier and a switch in the designed amplifier stage to enable the reconfiguration between the respective modes of operation. In addition, the output matching topology is designed to be symmetric for the corresponding amplifier stages with an input branch-line quadrature coupler and a unique harmonic tuning methodology that is used to effectively achieve a higher order load modulation in one of the modes, HLMBA. The other two modes of the PA stage are mismatch resilient and their performance is also observed to be efficient with switch settings dedicated to offer mismatch resilience at varied terminations

Broadband Linearity-Enhanced Doherty Power Amplifier Design Techniques for 5G Sub-6 GHz Applications

The recently deployed fifth generation (5G) cellular networks represent a significant technological advancement over fourth generation (4G) networks. Specifically, new 5G frequency bands were allocated at sub-6 GHz and instantaneous signal bandwidths were increased to satisfy the rapidly growing needs for increased data rates. Furthermore, 5G uses more complex modulation schemes to improve spectrum efficiency. Finally, 5G introduced massive multiple input multiple output (MIMO), where multiple transceivers are used to direct the signal towards specific users, increasing channel capacity. Conventional power amplifiers (PAs) are not suitable for 5G applications due to the increased signal and system complexity. For example, the Doherty power amplifier (DPA) technique is popular since DPAs can efficiently amplify signals with complex modulation schemes, but conventional DPAs have narrow bandwidth and poor linearity that preclude their use in 5G systems. This motivated research into DPA bandwidth and linearity improvements for use in 5G networks. This work focuses on bandwidth and linearity enhancement for sub-6 GHz DPAs realized using discrete components on a printed circuit board (PCB). Bandwidth is improved using broadband architectures for the DPA output combiner network (OCN), the absorption of drain parasitics, and broadband input matching network (IMN) design. Linearity is enhanced by proper drain biasing network design, and careful selection of transistor source impedances. A 3.3–5.0 GHz DPA using these techniques is designed and fabricated. Under wideband modulated signal excitation, the DPA offers very good linearity with appropriate digital predistortion (DPD). A 2×2 array of DPAs is evaluated in fully digital MIMO setup using a 2×2 antenna array. The DPA array achieves excellent linearity characteristics under 100 MHz signals and use of dual-input single-output (DISO) DPD. The DPA remains the ideal choice in 5G MIMO systems when compared to the class AB PA since it can maintain a higher average drain efficiency and similar linearity

Multi-Resonant Class-F Power Amplifier Design for 5G Cellular Networks

yesThis work integrates a harmonic tuning mechanism in synergy with the GaN HEMT transistor for 5G mobile transceiver applications. Following a theoretical study on the operational behavior of the Class-F power amplifier (PA), a complete amplifier design procedure is described that includes the proposed Harmonic Control Circuits for the second and third harmonics and optimum loading conditions for phase shifting of the drain current and voltage waveforms. The performance improvement provided by the Class-F configuration is validated by comparing the experimental and simulated results. The designed 10W Class-F PA prototype provides a measured peak drain efficiency of 64.7% at 1dB compression point of the PA at 3.6GHz frequency

Novel Predistortion System for 4G/5G Small-Cell and Wideband Transmitters

To meet the growing demand for mobile data, various technologies are being introduced to wireless networks to increase system capacity. On one hand, large number of small-cell base stations are adopted to serve the reduced cell size; on the other hand, millimeter wave (mm-wave) systems with large antenna arrays that transmit ultra-wideband signals are expected in fifth generation (5G) networks. Power amplifiers (PAs), responsible for boosting the radio frequency (RF) signal power, are the most critical components in base station transmitters, and dominate the overall efficiency and linearity of the system. The design challenges to balance the contradictory requirements of efficiency and linearity of the PAs are usually addressed by linearization techniques, particularly the digital predistortion (DPD) system. However, existing DPD solutions face increasing difficulties keeping up with new developments in base station technologies. When considering sub-6 GHz small-cell base station transmitters, analog and RF predistortion techniques have recently received renewed attention due to their inherent low power nature. Their achievable linearization capacity is significantly limited, however, largely by their implementation complexity in realizing the needed predistortion models in analog circuitry. On the other hand, despite significant developments in DPD models for wideband signals, the implementations of such DPD models in practical hardware have received relatively little attention. Yet the conventional implementation of a DPD engine is limited by the maximum clock frequency of the digital circuitry employed and cannot be scaled to satisfy the growing bandwidth of transmitted signals for 5G networks. Furthermore, both analog and digital solutions require a transmitter-observation-receiver (TOR) to capture the PA outputs, necessitates the use of analog-to-digital converters (ADCs) whose complexity and power consumption increase with signal bandwidth. Such trend is not scalable for future base stations, and new innovations in feedback and training methods are required. This thesis presents a number of contributions to address the above identified challenges. To reduce the power overhead of the linearization system, a digitally-assisted analog-RF predistortion (DA-ARFPD) system that uses a novel predistortion model is introduced. The proposed finite-impulse-response assisted envelope memory polynomial (FIR-EMP) model allows for a reduction of hardware implementation complexity while maintaining good linearization capacity and low power overhead. A two-step small-signal-assisted parameter identification (SSAPI) algorithm is devised to estimate the parameters of the two main blocks of the FIR-EMP model, such that the training can be completed efficiently. A DA-ARFPD test bench has been built, which incorporates major RF components, to assess the validity of the proposed FIR-EMP scheme and the SSAPI algorithm. Measurement results show that the proposed FIR-EMP model with SSAPI algorithm can successfully linearize multiple PAs driven with various wideband and carrier-aggregated signals of up to 80~MHz modulation bandwidths for sub-6 GHz systems. Next, a hardware-efficient real-time DPD system with scalable linearization bandwidth for ultra-wideband 5G mm-wave transmitters is proposed. It uses a novel parallel-processing DPD engine architecture to process multiple samples per clock cycle, overcomes the linearization bandwidth limit imposed by the maximum clock rate of digital circuits used in conventional DPD implementation. Potentially unlimited linearization bandwidth could be achieved by using the proposed system with current digital circuit technologies. The linearization performance and bandwidth scalability of the proposed system is demonstrated experimentally using a silicon-based Doherty (DPA) with 400 MHz wideband signal operating at 28 GHz, and over-the-air measurements using a 64-element beamforming array with 800 MHz wideband signal, also at 28 GHz. The proposed DPD system achieves over 2.4 GHz linearization bandwidth using only a 300 MHz core clock for the digital circuits. Finally, to reduce the power consumption and cost of the TOR, a new approach to train the predistorter using under-sampled feedback signal is presented. Using aliased samples of the PA's output captured at either baseband or intermedia frequency (IF), the proposed algorithm is able to compute the coefficients of the predistortion engine to linearize the PA using a direct learning architecture. Experimentally, both the baseband and IF schemes achieve linearization performance comparable to a full-rate system. Implemented together with a parallel-processing based DPD engine on a field-programmable gate array (FPGA) based system-on-chip (SOC), the proposed feedback and training solution achieves over 2.4~GHz linearization bandwidth using an ADC operating at a clock rate of 200 MHz. Its performance is demonstrated experimentally by linearizing a silicon DPA with 200 MHz and 400 MHz signals in conductive measurements, and a 64-element beamforming array with 400 MHz and 800 MHz signals in over-the-air testing