On the Virtualization of Audio Transducers

In audio transduction applications, virtualization can be defined as the task of digitally altering the acoustic behavior of an audio sensor or actuator with the aim of mimicking that of a target transducer. Recently, a digital signal preprocessing method for the virtualization of loudspeakers based on inverse equivalent circuit modeling has been proposed. The method applies Leuciuc’s inversion theorem to obtain the inverse circuital model of the physical actuator, which is then exploited to impose a target behavior through the so called Direct–Inverse–Direct Chain. The inverse model is designed by properly augmenting the direct model with a theoretical two-port circuit element called nullor. Drawing on this promising results, in this manuscript, we aim at describing the virtualization task in a broader sense, including both actuator and sensor virtualizations. We provide ready-to-use schemes and block diagrams which apply to all the possible combinations of input and output variables. We then analyze and formalize different versions of the Direct–Inverse–Direct Chain describing how the method changes when applied to sensors and actuators. Finally, we provide examples of applications considering the virtualization of a capacitive microphone and a nonlinear compression driver

Sensitivity Analysis and Distortion Decomposition of Mildly Nonlinear Circuits

Volterra Series (VS) is often used in the analysis of mildly nonlinear circuits. In this approach, nonlinear circuit analysis is converted into the analysis of a series of linear circuits. The main benefit of this approach is that linear circuit analysis is well established and direct frequency domain analysis of a nonlinear circuit becomes possible. Sensitivity analysis is useful in comparing the quality of two designs and the evaluation of gradient, Jacobian or Hessian matrices, in analog Computer Aided Design. This thesis presents, for the first time, the sensitivity analysis of mildly nonlinear circuits in the frequency domain as an extension of the VS approach. To overcome efficiency limitation due to multiple mixing effects, Nonlinear Transfer Matrix (NTM) is introduced. It is the first explicit analytical representation of the complicated multiple mixing effects. The application of NTM in sensitivity analysis is capable of two orders of magnitude speedup. Per-element distortion decomposition determines the contribution towards the total distortion from an individual nonlinearity. It is useful in design optimization, symbolic simplification and nonlinear model reduction. In this thesis, a numerical distortion decomposition technique is introduced which combines the insight of traditional symbolic analysis with the numerical advantages of SPICE like simulators. The use of NTM leads to an efficient implementation. The proposed method greatly extends the size of the circuit and the complexity of the transistor model over what previous approaches could handle. For example, industry standard compact model, such as BSIM3V3 [35] was used for the first time in distortion analysis. The decomposition can be achieved at device, transistor and block level, all with device level accuracy. The theories have been implemented in a computer program and validated on examples. The proposed methods will leverage the performance of present VS based distortion analysis to the next level

Modeling and Simulation Techniques for Microwave Components

This chapter discusses about methods used in simulation and modeling of radio frequency (RF)/microwave circuits and components. The main topic that is discussed here is about one of the most powerful methods, that is, artificial neural networks. In this chapter, different types of neural network such as dynamic and recurrent neural networks will be discussed. Other techniques that are popular in the area of microwave components simulation and modeling are numerical techniques such as vector fitting, Krylov method, and Pade approximation. At the end of the chapter, vector fitting as an example of numerical methods will be discussed

Automated analysis, design, and optimization of low noise oscillators

Low noise oscillators are universally needed in digital systems for clock generation and synchronization, and in radio-frequency communication front-ends for frequency up- and down-conversion. Noise in oscillators results in timing jitter, and limits the clock frequency of digital systems. In radio-frequency communication systems, phase noise in oscillators lowers the signal-to-noise ratio of transmitters and receivers, and degrades the overall bit-error-rate. Therefore, accurate simulation and optimization of oscillator noise performance is of utmost importance. The focus of this dissertation is on automated analysis, design and optimization of low noise oscillators. Several advances in oscillator analysis that facilitate automated oscillator design and optimization are presented. These include a new sensitivity analysis for oscillators, a design-oriented circuit analysis technique, and an oscillator design optimization approach. The sensitivity analysis calculates sensitivities of an oscillator's periodic steady-state and perturbation projection vector to design, process, or environmental parameters. In the design-oriented approach to circuit analysis the circuit response is computed together with the values of circuit parameters that result in a desired circuit performance. These analyses form the foundation for an efficient oscillator optimization technique that is general and applicable to all oscillator types.Keywords: simulation, circuit, analysis, sensitivity, optimization, design, oscillato

SCEE 2008 book of abstracts : the 7th International Conference on Scientific Computing in Electrical Engineering (SCEE 2008), September 28 – October 3, 2008, Helsinki University of Technology, Espoo, Finland

This report contains abstracts of presentations given at the SCEE 2008 conference.reviewe

Advanced modeling of nanoscale devices for analog applications

L'abstract è presente nell'allegato / the abstract is in the attachmen

Center for Space Microelectronics Technology. 1993 Technical Report

The 1993 Technical Report of the Jet Propulsion Laboratory Center for Space Microelectronics Technology summarizes the technical accomplishments, publications, presentations, and patents of the Center during the past year. The report lists 170 publications, 193 presentations, and 84 New Technology Reports and patents. The 1993 Technical Report of the Jet Propulsion Laboratory Center for Space Microelectronics Technology summarizes the technical accomplishments, publications, presentations, and patents of the Center during the past year. The report lists 170 publications, 193 presentations, and 84 New Technology Reports and patents

Electromagnetics-Based Design Using Artificial Neural Networks

This Chapter aims at reviewing the relevant work in electromagnetics-based design and optimization of RF and microwave circuits exploiting artificial neural networks (ANNs). Measurement-based design of high-speed circuits using ANNs is also treated

Saw-Less radio receivers in CMOS

Smartphones play an essential role in our daily life. Connected to the internet, we can easily keep in touch with family and friends, even if far away, while ever more apps serve us in numerous ways. To support all of this, higher data rates are needed for ever more wireless users, leading to a very crowded radio frequency spectrum. To achieve high spectrum efficiency while reducing unwanted interference, high-quality band-pass filters are needed. Piezo-electrical Surface Acoustic Wave (SAW) filters are conventionally used for this purpose, but such filters need a dedicated design for each new band, are relatively bulky and also costly compared to integrated circuit chips. Instead, we would like to integrate the filters as part of the entire wireless transceiver with digital smartphone hardware on CMOS chips. The research described in this thesis targets this goal. It has recently been shown that N-path filters based on passive switched-RC circuits can realize high-quality band-select filters on CMOS chips, where the center frequency of the filter is widely tunable by the switching-frequency. As CMOS downscaling following Moore’s law brings us lower clock-switching power, lower switch on-resistance and more compact metal-to-metal capacitors, N-path filters look promising. This thesis targets SAW-less wireless receiver design, exploiting N-path filters. As SAW-filters are extremely linear and selective, it is very challenging to approximate this performance with CMOS N-path filters. The research in this thesis proposes and explores several techniques for extending the linearity and enhancing the selectivity of N-path switched-RC filters and mixers, and explores their application in CMOS receiver chip designs. First the state-of-the-art in N-path filters and mixer-first receivers is reviewed. The requirements on the main receiver path are examined in case SAW-filters are removed or replaced by wideband circulators. The feasibility of a SAW-less Frequency Division Duplex (FDD) radio receiver is explored, targeting extreme linearity and compression Irequirements. A bottom-plate mixing technique with switch sharing is proposed. It improves linearity by keeping both the gate-source and gate-drain voltage swing of the MOSFET-switches rather constant, while halving the switch resistance to reduce voltage swings. A new N-path switch-RC filter stage with floating capacitors and bottom-plate mixer-switches is proposed to achieve very high linearity and a second-order voltage-domain RF-bandpass filter around the LO frequency. Extra out-of-band (OOB) rejection is implemented combined with V-I conversion and zero-IF frequency down-conversion in a second cross-coupled switch-RC N-path stage. It offers a low-ohmic high-linearity current path for out-of-band interferers. A prototype chip fabricated in a 28 nm CMOS technology achieves an in-band IIP3 of +10 dBm , IIP2 of +42 dBm, out-of-band IIP3 of +44 dBm, IIP2 of +90 dBm and blocker 1-dB gain-compression point of +13 dBm for a blocker frequency offset of 80 MHz. At this offset frequency, the measured desensitization is only 0.6 dB for a 0-dBm blocker, and 3.5 dB for a 10-dBm blocker at 0.7 GHz operating frequency (i.e. 6 and 9 dB blocker noise figure). The chip consumes 38-96 mW for operating frequencies of 0.1-2 GHz and occupies an active area of 0.49 mm2. Next, targeting to cover all frequency bands up to 6 GHz and achieving a noise figure lower than 3 dB, a mixer-first receiver with enhanced selectivity and high dynamic range is proposed. Capacitive negative feedback across the baseband amplifier serves as a blocker bypassing path, while an extra capacitive positive feedback path offers further blocker rejection. This combination of feedback paths synthesizes a complex pole pair at the input of the baseband amplifier, which is up-converted to the RF port to obtain steeper RF-bandpass filter roll-off than the conventional up-converted real pole and reduced distortion. This thesis explains the circuit principle and analyzes receiver performance. A prototype chip fabricated in 45 nm Partially Depleted Silicon on Insulator (PDSOI) technology achieves high linearity (in-band IIP3 of +3 dBm, IIP2 of +56 dBm, out-of-band IIP3 = +39 dBm, IIP2 = +88 dB) combined with sub-3 dB noise figure. Desensitization due to a 0-dBm blocker is only 2.2 dB at 1.4 GHz operating frequency. IIFinally, to demonstrate the performance of the implemented blocker-tolerant receiver chip designs, a test setup with a real mobile phone is built to verify the sensitivity of the receiver chip for different practical blocking scenarios