6 research outputs found
Efficient Dual-ISA Support in a Retargetable, Asynchronous Dynamic Binary Translator
Dynamic Binary Translation (DBT) allows software compiled for one Instruction Set Architecture (ISA) to be executed on a processor supporting a different ISA. Some modern DBT systems decouple their main execution loop from the built-inJust-In-Time (JIT) compiler, i.e. the JIT compiler can operate asynchronously in a different thread without blocking program execution. However, this creates a problem for target architectures with dual-ISA support such as ARM/THUMB, where the ISA of the currently executed instruction stream may be different to the one processed by the JIT compiler due to their decoupled operation and dynamic mode changes. In this paper we present a new approach for dual-ISA support in such an asynchronous DBT system, which integrates ISA mode tracking and hot-swapping of software instruction decoders. We demonstrate how this can be achieved in a retargetable DBT system, where the target ISA is not hard-coded, but a processor-specific module is generated from a high-level architecture description. We have implemented ARM V5T support in our DBT and demonstrate execution rates of up to 1148 MIPS for the SPEC CPU 2006 benchmarks compiled for ARM/THUMB, achieving on average 192%, and up to 323%, of the speed of QEMU, which has been subject to intensive manual performance tuning and requires significant low-level effort for retargeting
FAT-DBT engine (framework for application-tailorcd, co-designcd dynamic binary translation enginc)
Tese de Doutoramento em Engenharia Eletrónica e de Computadores (PDEEC)Dynamic binary translation (DBT) has emerged as an execution engine that monitors,
modifies and possibly optimizes running applications for specific purposes.
DBT is deployed as an execution layer between the application binary and the operating
system or host-machine, which creates opportunities for collecting runtime
information. Initially, DBT supported binary-level compatibility, but based on the
collected runtime information, it also became popular for code instrumentation,
ISA-virtualization and dynamic-optimization purposes.
Building a DBT system brings many challenges, as it involves complex components
integration and requires deep architectural level knowledge. Moreover, DBT incurs
in significant overheads, mainly due to code decoding and translation, as well as
execution along with general functionalities emulation. While initially conceived
bearing in mind high-end architectures for performance demanding applications,
such challenges become even more evident when directing DBT to embedded systems.
The latter makes an effective deployment very challenging due to its complexity,
tight constraints on memory, and limited performance and power. Legacy
support and binary compatibility is a topic of relevant interest in such systems,
due to their broad dissemination among industrial environments and wide utilization
in sensing and monitoring processes, from yearly times, with considerable
maintenance and replacement costs.
To address such issues, this thesis intents to contribute with a solution that leverages
an optimized and accelerated dynamic binary translator targeting resourceconstrained
embedded systems while supporting legacy systems.
The developed work allows to: (1) evaluate the potential of DBT for legacy support
purposes on the resource-constrained embedded systems; (2) achieve a configurable
DBT architecture specialized for resource-constrained embedded systems;
(3) address DBT translation, execution and emulation overheads through the combination
of software and hardware; and (4) promote DBT utilization as a legacy
support tool for the industry as a end-product.A tradução binária dinâmica (TBD) emergiu como um motor de execução que
permite a modificação e possível optimização de código executável para um determinado
propósito. A TBD é integrada nos sistemas como uma camada de execução
entre o código binário executável e o sistema operativo ou a máquina hospedeira
alvo, o que origina oportunidades de recolha de informação de execução.
A criação de um sistema de TBD traz consigo diversos desafios, uma vez que envolve
a integração de componentes complexos e conhecimentos aprofundados das
arquitecturas de processadores envolvidas. Ademais, a utilização de TBD gera diversos
custos computacionais indirectos, maioritariamente devido à descodificação
e tradução de código, bem como emulação de funcionalidades em geral. Considerando
que a TBD foi inicialmente pensada para sistemas de gama alta, os
desafios mencionados tornam-se ainda mais evidentes quando a mesma é aplicada
em sistemas embebidos. Nesta área os limitados recursos de memória e os exigentes
requisitos de desempenho e consumo energético,tornam uma implementação eficiente
de TBD muito difícil de obter. Compatibilidade binária e suporte a código
de legado são tópicos de interesse em sistemas embebidos, justificado pela ampla
disseminação dos mesmos no meio industrial para tarefas de sensorização e monitorização
ao longo dos tempos, reforçado pelos custos de manutenção adjacentes
à sua utilização.
Para endereçar os desafios descritos, nesta tese propõe-se uma solução para potencializar
a tradução binária dinâmica, optimizada e com aceleração, para suporte a
código de legado em sistemas embebidos de baixa gama.
O trabalho permitiu (1) avaliar o potencial da TBD quando aplicada ao suporte
a código de legado em sistemas embebidos de baixa gama; (2) a obtenção de
uma arquitectura de TBD configurável e especializada para este tipo de sistemas;
(3) reduzir os custos computacionais associados à tradução, execução e emulação,
através do uso combinado de software e hardware; (4) e promover a utilização na
industria de TBD como uma ferramenta de suporte a código de legado.This thesis was supported by a PhD scholarship from Fundação para a Ciência e
Tecnologia, SFRH/BD/81681/201
Efficient cross-architecture hardware virtualisation
Hardware virtualisation is the provision of an isolated virtual environment that
represents real physical hardware. It enables operating systems, or other system-level
software (the guest), to run unmodified in a “container” (the virtual machine)
that is isolated from the real machine (the host).
There are many use-cases for hardware virtualisation that span a wide-range
of end-users. For example, home-users wanting to run multiple operating systems
side-by-side (such as running a Windows® operating system inside an OS
X environment) will use virtualisation to accomplish this. In research and development
environments, developers building experimental software and hardware
want to prototype their designs quickly, and so will virtualise the platform
they are targeting to isolate it from their development workstation. Large-scale
computing environments employ virtualisation to consolidate hardware, enforce
application isolation, migrate existing servers or provision new servers.
However, the majority of these use-cases call for same-architecture virtualisation,
where the architecture of the guest and the host machines match—a situation
that can be accelerated by the hardware-assisted virtualisation extensions
present on modern processors. But, there is significant interest in virtualising
the hardware of different architectures on a host machine, especially in the
architectural research and development worlds.
Typically, the instruction set architecture of a guest platform will be different
to the host machine, e.g. an ARM guest on an x86 host will use an ARM instruction
set, whereas the host will be using the x86 instruction set. Therefore, to
enable this cross-architecture virtualisation, each guest instruction must be emulated
by the host CPU—a potentially costly operation. This thesis presents a
range of techniques for accelerating this instruction emulation, improving over
a state-of-the art instruction set simulator by 2:64x. But, emulation of the guest
platform’s instruction set is not enough for full hardware virtualisation. In fact,
this is just one challenge in a range of issues that must be considered. Specifically,
another challenge is efficiently handling the way external interrupts are
managed by the virtualisation system. This thesis shows that when employing
efficient instruction emulation techniques, it is not feasible to arbitrarily
divert control-flow without consideration being given to the state of the emulated
processor. Furthermore, it is shown that it is possible for the virtualisation
environment to behave incorrectly if particular care is not given to the point
at which control-flow is allowed to diverge. To solve this, a technique is developed
that maintains efficient instruction emulation, and correctly handles
external interrupt sources.
Finally, modern processors have built-in support for hardware virtualisation
in the form of instruction set extensions that enable the creation of an abstract
computing environment, indistinguishable from real hardware. These extensions
enable guest operating systems to run directly on the physical processor,
with minimal supervision from a hypervisor. However, these extensions are
geared towards same-architecture virtualisation, and as such are not immediately
well-suited for cross-architecture virtualisation. This thesis presents a
technique for exploiting these existing extensions, and using them in a cross-architecture
virtualisation setting, improving the performance of a novel cross-architecture
virtualisation hypervisor over state-of-the-art by 2:5x
Addressing the Challenges of DBT for the ARM Architecture
Dynamic binary translation (DBT) can provide security, virtualization, resource management and other desirable services to embedded systems. Although DBT has many benefits, its run-time performance overhead can be relatively high. The run-time overhead is important in embedded systems due to their slow processor clock speeds,simple microarchitectures, and small caches.This paper addresses how to implement efficient DBT for ARM-based embedded systems, taking into account instruction set and cache/TLB nuances. We develop several techniques that reduce DBT overhead for the ARM. Our techniques focus on cache and TLB behavior. We tested the techniques on an ARM-based embedded device and found that DBT overhead was reduced by 54 % in comparison to a general-purpose DBT configuration that is known to perform well, thus further enabling DBT for a wide range of purposes. Categories and Subject Descriptors C.3 [Computer Systems Organization]: Special-purpose and application- based systems–Realtime and embedded systems; D.3.4 [Programming Languages]: Processors–Code generation, Compilers, Incremental compilers