High Performance Power Management Integrated Circuits for Portable Devices

abstract: Portable devices often require multiple power management IC (PMIC) to power different sub-modules, Li-ion batteries are well suited for portable devices because of its small size, high energy density and long life cycle. Since Li-ion battery is the major power source for portable device, fast and high-efficiency battery charging solution has become a major requirement in portable device application. In the first part of dissertation, a high performance Li-ion switching battery charger is proposed. Cascaded two loop (CTL) control architecture is used for seamless CC-CV transition, time based technique is utilized to minimize controller area and power consumption. Time domain controller is implemented by using voltage controlled oscillator (VCO) and voltage controlled delay line (VCDL). Several efficiency improvement techniques such as segmented power-FET, quasi-zero voltage switching (QZVS) and switching frequency reduction are proposed. The proposed switching battery charger is able to provide maximum 2 A charging current and has an peak efficiency of 93.3%. By configure the charger as boost converter, the charger is able to provide maximum 1.5 A charging current while achieving 96.3% peak efficiency. The second part of dissertation presents a digital low dropout regulator (DLDO) for system on a chip (SoC) in portable devices application. The proposed DLDO achieve fast transient settling time, lower undershoot/overshoot and higher PSR performance compared to state of the art. By having a good PSR performance, the proposed DLDO is able to power mixed signal load. To achieve a fast load transient response, a load transient detector (LTD) enables boost mode operation of the digital PI controller. The boost mode operation achieves sub microsecond settling time, and reduces the settling time by 50% to 250 ns, undershoot/overshoot by 35% to 250 mV and 17% to 125 mV without compromising the system stability.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

Improved Accuracy Area Efficient Hybrid CMOS/GaN DC-DC Buck Converterfor High Step-Down Ratio Applications

abstract: Point of Load (POL) DC-DC converters are increasingly used in space applications, data centres, electric vehicles, portable computers and devices and medical electronics. Heavy computing and processing capabilities of the modern devices have ushered the use of higher battery supply voltage to increase power storage. The need to address this consumer experience driven requirement has propelled the evolution of the next generation of small form-factor power converters which can operate with higher step down ratios while supplying heavy continuous load currents without sacrificing efficiency. Constant On-Time (COT) converter topology is capable of achieving stable operation at high conversion ratio with minimum off-chip components and small silicon area. This work proposes a Constant On-Time buck dc-dc converter for a wide dynamic input range and load currents from 100mA to 10A. Accuracy of this ripple based converter is improved by a unique voltage positioning technique which modulates the reference voltage to lower the average ripple profile close to the nominal output. Adaptive On-time block features a transient enhancement scheme to assist in faster voltage droop recovery when the output voltage dips below a defined threshold. UtilizingGallium Nitride (GaN) power switches enable the proposed converter to achieve very high efficiency while using smaller size inductor-capacitor (LC) power-stage. Use of novel Superjunction devices with higher drain-source blocking voltage simplifies the complex driver design and enables faster frequency of operation. It allows 1.8VComplementary Metal-Oxide Semiconductor (CMOS) devices to effectively drive GaNpower FETs which require 5V gate signal swing. The presented controller circuit uses internal ripple generation which reduces reliance on output cap equivalent series resistance (ESR) for loop stability and facilitates ripples reduction at the output. The ripple generation network is designed to provide ai optimally stable performance while maintaining load regulation and line regulation accuracy withing specified margin. The chip with ts external Power FET package is proposed to be integrated on a printed circuit board for testing. The designed power converter is expected to operate under 200 MRad of a total ionising dose of radiation enabling it to function within large hadron collider at CERN and space satellite and probe missions.Dissertation/ThesisMasters Thesis Electrical Engineering 201

Energy efficient control for power management circuits operating from nano-watts to watts

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2013.Cataloged from PDF version of thesis.Includes bibliographical references (p. 163-172).Energy efficiency and form factor are the key driving forces in today's power electronics. All power delivery circuits, irrespective of the magnitude of power, basically consists of power trains, gate drivers and control circuits. Although the control circuits are primarily required for regulation, these circuits can play a crucial role in achieving high efficiency and/or minimizing overall system form-factor. In this thesis, power converter circuits, spanning a wide operating range- from nano-watts to watts, are presented while highlighting techniques for using digital control circuits not just for regulation but also to achieve high system efficiency and smaller system form-factor. The first part of the thesis presents a power management unit of an autonomous wireless sensor that sustains itself by harvesting energy from the endo-cochlear potential (EP), the 70-100mV electrochemical potential inside the mammalian inner ear. Due to the anatomical constraints, the total extractable power from the EP is limited to 1.1-6.3nW. A low switching frequency boost converter is employed to increase the input voltage to a higher voltage usable by CMOS circuits in the sensor. Ultra-low power digital control circuits with timers help keep the quiescent power of the power management unit down to 544pW. Further, a charge-pump is used to implement leakage reduction techniques in the sensor. This work demonstrates how digital low power control circuit design can help improve converter efficiency and ensure system sustainability. All circuits have been implemented on a 0.18[mu]m CMOS process. The second part of the thesis discusses an energy harvesting architecture that combines energy from multiple energy harvesting sources- photovoltaic, thermoelectric and piezoelectric sources. Digital control circuits that configure the power trains to new efficient system architectures with maximum power point tracking are presented, while using a single inductor to combine energy from the aforementioned energy sources all at the same time. A dual-path architecture for energy harvesting systems is proposed. This provides a peak efficiency improvement of 11-13% over the traditional two stage approach. The system can handle input voltages from 20mV to 5V and is also capable of extracting maximum power from individual harvesters all at the same time utilizing a single inductor. A proposed completely digital timebased power monitor is used for achieving maximum power point tracking for the photovoltaic harvester. This has a peak tracking efficiency of 96%. The peak efficiencies achieved with inductor sharing are 83%, 58% and 79% for photovoltaic boost, thermoelectric boost and piezoelectric buck-boost converters respectively. The switch matrix and the control circuits are implemented on a 0.35pm CMOS process. This part of the thesis highlights how digital control circuits can help reconfigure power converter architectures for improving efficiency and reducing form-factors. The last part of the thesis deals with a power management system for an offline 22W LED driver. In order to reduce the system form factor, Gallium Nitride (GaN) transistors capable of high frequency switching have been utilized with a Quasi-Resonant Inverted Buck architecture. A burst mode digital controller has been used to perform dimming control and power factor correction (PFC) for the LED driver. The custom controller and driver IC was implemented in a 0.35[mu]m CMOS process. The LED driver achieves a peak efficiency of 90.6% and a 0.96 power factor. Due to the high power level of the driver, the digital controller is primarily used for regulation purposes in this system, although the digital nature of the controller helps remove the passives that would be normally present in analog controllers. In this thesis, apart from regulation, control circuit enabled techniques have been used to improve efficiency and reduce system form factor. Low power design and control for reconfigurable power train architectures help improve the overall power converter efficiency. Digital control circuits have been used to reduce the form factor by enabling inductor sharing in a system with multiple power converters or by removing the compensator passives.by Saurav Bandyopadhyay.Ph.D

Power Management Electronics

Accepted versio

Double Resonant High-Frequency Converters for Wireless Power Transfer

This thesis describes novel techniques and developments in the design and implementation of a low power radio frequency (40kHz to 1MHz) wireless power transfer (WPT) system, with an application in the wireless charging of autonomous drones without physical connection to its on-board Battery Management System (BMS). The WPT system is developed around a matrix converter exploiting the benefits such as a small footprint (DC-link free), high efficiency and high power density. The overall WPT system topology discussed in this thesis is based on the current state-of-the-art found in literature, but enhancements are made through novel methods to further improve the converter’s stability, reduce control complexity and improve the wireless power efficiency. In this work, each part of the system is analysed and novel techniques are proposed to achieve improvements. The WPT system design methodology presented in this thesis commences with the use of a conventional full-bridge converter. For cost-efficiency and to improve the converters stability, a novel gate drive circuit is presented which provides self-generated negative bias such that a bipolar MOSFET drive can be driven without an additional voltage source or magnetic component. The switching control sequences for both a full-bridge and single phase to single phase matrix converter are analysed which show that the switching of a matrix converter can be considered to be the same as a full-bridge converter under certain conditions. A middleware is then presented that reduces the complexity of the control required for a matrix converter and enables control by a conventional full-bridge controller (i.e. linear controller or microcontroller). A novel technique that can maximise and maintain in real-time the WPT efficiency is presented using a maximum efficiency point tracking approach. A detailed study of potential issues that may affect the implementation of this novel approach are presented and new solutions are proposed. A novel wireless pseudo-synchronous sampling method is presented and implemented on a prototype system to realise the maximum efficiency point tracking approach. Finally, a new hybrid wireless phase-locked loop is presented and implemented to minimise the bandwidth requirements of the maximum efficiency point tracking approach. The performance and methods for implementation of the novel concepts introduced in this thesis are demonstrated through a number of prototypes that were built. These include a matrix converter and two full WPT systems with operating frequencies ranging from sub-megahertz to megahertz level. Moreover, the final prototype is applied to the charging of a quadcopter battery pack to successfully charge the pack wirelessly whilst actively balancing the cells. Hence, fast battery charging and cell balancing, which conventionally requires battery removal, can be achieved without re-balance the weight of the UAV