Digitally-Enhanced Software-Defined Radio Receiver Robust to Out-of-Band Interference

A software-defined radio (SDR) receiver with improved robustness to out-of-band interference (OBI) is presented. Two main challenges are identified for an OBI-robust SDR receiver: out-of-band nonlinearity and harmonic mixing. Voltage gain at RF is avoided, and instead realized at baseband in combination with low-pass filtering to mitigate blockers and improve out-of-band IIP3. Two alternative “iterative” harmonic-rejection (HR) techniques are presented to achieve high HR robust to mismatch: a) an analog two-stage polyphase HR concept, which enhances the HR to more than 60 dB; b) a digital adaptive interference cancelling (AIC) technique, which can suppress one dominating harmonic by at least 80 dB. An accurate multiphase clock generator is presented for a mismatch-robust HR. A proof-of-concept receiver is implemented in 65 nm CMOS. Measurements show 34 dB gain, 4 dB NF, and 3.5 dBm in-band IIP3 while the out-of-band IIP3 is + 16 dBm without fine tuning. The measured RF bandwidth is up to 6 GHz and the 8-phase LO works up to 0.9 GHz (master clock up to 7.2 GHz). At 0.8 GHz LO, the analog two-stage polyphase HR achieves a second to sixth order HR > dB over 40 chips, while the digital AIC technique achieves HR > 80 dB for the dominating harmonic. The total power consumption is 50 mA from a 1.2 V supply

Equalization of Third-Order Intermodulation Products in Wideband Direct Conversion Receivers

This paper reports a SAW-less direct-conversion receiver which utilizes a mixed-signal feedforward path to regenerate and adaptively cancel IM3 products, thus accomplishing system-level linearization. The receiver system performance is dominated by a custom integrated RF front end implemented in 130-nm CMOS and achieves an uncorrected out-of-band IIP3 of -7.1 dBm under the worst-case UMTS FDD Region 1 blocking specifications. Under IM3 equalization, the receiver achieves an effective IIP3 of +5.3 dBm and meets the UMTS BER sensitivity requirement with 3.7 dB of margin

Development of Robust Analog and Mixed-Signal Circuits in the Presence of Process- Voltage-Temperature Variations

Continued improvements of transceiver systems-on-a-chip play a key role in the advancement of mobile telecommunication products as well as wireless systems in biomedical and remote sensing applications. This dissertation addresses the problems of escalating CMOS process variability and system complexity that diminish the reliability and testability of integrated systems, especially relating to the analog and mixed-signal blocks. The proposed design techniques and circuit-level attributes are aligned with current built-in testing and self-calibration trends for integrated transceivers. In this work, the main focus is on enhancing the performances of analog and mixed-signal blocks with digitally adjustable elements as well as with automatic analog tuning circuits, which are experimentally applied to conventional blocks in the receiver path in order to demonstrate the concepts. The use of digitally controllable elements to compensate for variations is exemplified with two circuits. First, a distortion cancellation method for baseband operational transconductance amplifiers is proposed that enables a third-order intermodulation (IM3) improvement of up to 22dB. Fabricated in a 0.13µm CMOS process with 1.2V supply, a transconductance-capacitor lowpass filter with the linearized amplifiers has a measured IM3 below -70dB (with 0.2V peak-to-peak input signal) and 54.5dB dynamic range over its 195MHz bandwidth. The second circuit is a 3-bit two-step quantizer with adjustable reference levels, which was designed and fabricated in 0.18µm CMOS technology as part of a continuous-time SigmaDelta analog-to-digital converter system. With 5mV resolution at a 400MHz sampling frequency, the quantizer's static power dissipation is 24mW and its die area is 0.4mm^2. An alternative to electrical power detectors is introduced by outlining a strategy for built-in testing of analog circuits with on-chip temperature sensors. Comparisons of an amplifier's measurement results at 1GHz with the measured DC voltage output of an on-chip temperature sensor show that the amplifier's power dissipation can be monitored and its 1-dB compression point can be estimated with less than 1dB error. The sensor has a tunable sensitivity up to 200mV/mW, a power detection range measured up to 16mW, and it occupies a die area of 0.012mm^2 in standard 0.18µm CMOS technology. Finally, an analog calibration technique is discussed to lessen the mismatch between transistors in the differential high-frequency signal path of analog CMOS circuits. The proposed methodology involves auxiliary transistors that sense the existing mismatch as part of a feedback loop for error minimization. It was assessed by performing statistical Monte Carlo simulations of a differential amplifier and a double-balanced mixer designed in CMOS technologies

Dirty RF Signal Processing for Mitigation of Receiver Front-end Non-linearity

Moderne drahtlose Kommunikationssysteme stellen hohe und teilweise gegensätzliche Anforderungen an die Hardware der Funkmodule, wie z.B. niedriger Energieverbrauch, große Bandbreite und hohe Linearität. Die Gewährleistung einer ausreichenden Linearität ist, neben anderen analogen Parametern, eine Herausforderung im praktischen Design der Funkmodule. Der Fokus der Dissertation liegt auf breitbandigen HF-Frontends für Software-konfigurierbare Funkmodule, die seit einigen Jahren kommerziell verfügbar sind. Die praktischen Herausforderungen und Grenzen solcher flexiblen Funkmodule offenbaren sich vor allem im realen Experiment. Eines der Hauptprobleme ist die Sicherstellung einer ausreichenden analogen Performanz über einen weiten Frequenzbereich. Aus einer Vielzahl an analogen Störeffekten behandelt die Arbeit die Analyse und Minderung von Nichtlinearitäten in Empfängern mit direkt-umsetzender Architektur. Im Vordergrund stehen dabei Signalverarbeitungsstrategien zur Minderung nichtlinear verursachter Interferenz - ein Algorithmus, der besser unter "Dirty RF"-Techniken bekannt ist. Ein digitales Verfahren nach der Vorwärtskopplung wird durch intensive Simulationen, Messungen und Implementierung in realer Hardware verifiziert. Um die Lücken zwischen Theorie und praktischer Anwendbarkeit zu schließen und das Verfahren in reale Funkmodule zu integrieren, werden verschiedene Untersuchungen durchgeführt. Hierzu wird ein erweitertes Verhaltensmodell entwickelt, das die Struktur direkt-umsetzender Empfänger am besten nachbildet und damit alle Verzerrungen im HF- und Basisband erfasst. Darüber hinaus wird die Leistungsfähigkeit des Algorithmus unter realen Funkkanal-Bedingungen untersucht. Zusätzlich folgt die Vorstellung einer ressourceneffizienten Echtzeit-Implementierung des Verfahrens auf einem FPGA. Abschließend diskutiert die Arbeit verschiedene Anwendungsfelder, darunter spektrales Sensing, robuster GSM-Empfang und GSM-basiertes Passivradar. Es wird gezeigt, dass nichtlineare Verzerrungen erfolgreich in der digitalen Domäne gemindert werden können, wodurch die Bitfehlerrate gestörter modulierter Signale sinkt und der Anteil nichtlinear verursachter Interferenz minimiert wird. Schließlich kann durch das Verfahren die effektive Linearität des HF-Frontends stark erhöht werden. Damit wird der zuverlässige Betrieb eines einfachen Funkmoduls unter dem Einfluss der Empfängernichtlinearität möglich. Aufgrund des flexiblen Designs ist der Algorithmus für breitbandige Empfänger universal einsetzbar und ist nicht auf Software-konfigurierbare Funkmodule beschränkt.Today's wireless communication systems place high requirements on the radio's hardware that are largely mutually exclusive, such as low power consumption, wide bandwidth, and high linearity. Achieving a sufficient linearity, among other analogue characteristics, is a challenging issue in practical transceiver design. The focus of this thesis is on wideband receiver RF front-ends for software defined radio technology, which became commercially available in the recent years. Practical challenges and limitations are being revealed in real-world experiments with these radios. One of the main problems is to ensure a sufficient RF performance of the front-end over a wide bandwidth. The thesis covers the analysis and mitigation of receiver non-linearity of typical direct-conversion receiver architectures, among other RF impairments. The main focus is on DSP-based algorithms for mitigating non-linearly induced interference, an approach also known as "Dirty RF" signal processing techniques. The conceived digital feedforward mitigation algorithm is verified through extensive simulations, RF measurements, and implementation in real hardware. Various studies are carried out that bridge the gap between theory and practical applicability of this approach, especially with the aim of integrating that technique into real devices. To this end, an advanced baseband behavioural model is developed that matches to direct-conversion receiver architectures as close as possible, and thus considers all generated distortions at RF and baseband. In addition, the algorithm's performance is verified under challenging fading conditions. Moreover, the thesis presents a resource-efficient real-time implementation of the proposed solution on an FPGA. Finally, different use cases are covered in the thesis that includes spectrum monitoring or sensing, GSM downlink reception, and GSM-based passive radar. It is shown that non-linear distortions can be successfully mitigated at system level in the digital domain, thereby decreasing the bit error rate of distorted modulated signals and reducing the amount of non-linearly induced interference. Finally, the effective linearity of the front-end is increased substantially. Thus, the proper operation of a low-cost radio under presence of receiver non-linearity is possible. Due to the flexible design, the algorithm is generally applicable for wideband receivers and is not restricted to software defined radios

Implementation of DSP-based algorithms on USRP for mitigating non-linear distortions in the receiver

In recent years, software-defined radio (SDR) has attracted increasingly more attention in regards to modern communication systems. The concept of SDR defines a radio device that is capable of flexibly reconfiguring its radio interface by software. This opens multiple fields of application and makes SDR an enormously adjustable and versatile radio technology. However, RF impairments induced by cheap and simple RF front-ends turn out to be a significant limitation in practice. Non-linear distortions emerge from non-linear components of the direct down-conversion chain that are driven into their saturation level. This is a result of a finite linearity and limited dynamic range of the RF frontend. The focus of this thesis are non-linear distortions in wideband receivers and a mitigation of them by means of digital signal processing. The idea is to artificially regenerate the non-linear distortions in the digital domain by applying a memoryless, polynomial model. An adaptive filter adjusts these reference distortions in their magnitude and phase and subtracts them from the distorted signal. A hardware implementation of a mitigation algorithm on a typical SDR-platform is presented. No prior implementation of this pure-digital approach is known. An implementation design flow is described following a top-down approach, starting from a fixed-point high-level implementation and ending up with a low-level hardware description language implementation. Both high-level and low-level simulations help to validate and evaluate the implementation. In conclusion, the implementation of the mitigation algorithm is a sophisticated mitigation technique for cleaning a down-converted baseband spectrum of non-linear distortions in real-time. Therefore, the effective linearity of the RF front-end is increased. This may lead to a significant improvement in the bit error rate performance of cleansed modulated signals, as well as to an enhanced sensing reliability in the context of cognitive radio.Zusammenfassung: In den letzten Jahren sorgte Software-Defined Radio (SDR) in Bezug auf moderne Kommunikationssysteme für immer größere Aufmerksamkeit. Das Konzept von SDR bezeichnet ein Funkgerät, das in der Lage ist, seine Funkschnittstelle durch Software flexibel zu rekonfigurieren. Dies ermöglicht eine Vielzahl von Anwendungsmöglichkeiten und macht SDR zu einer enorm anpassungsfähigen und vielseitigen Funktechnologie. Allerdings stellen im HF-Frontend ausgelöste Störungen in der Praxis eine erhebliche Einschränkung dar. In direkt umsetzenden Empfängerstrukturen entstehen durch nichtlineare Komponenten, die in ihren Sättigungsbereich getrieben werden, nichtlineare Verzerrungen. Das ist ein Ergebnis der begrenzten Linearität und des Dynamikbereich des HF-Frontends eingeschränkt sind. Der Fokus der Arbeit liegt auf nichtlinearen Verzerrungen in breitbandigen Empfängern und deren Minderung mit Hilfe von digitaler Signalverarbeitung. Die Idee ist, die nichtlinearen Verzerrungen im digitalen Bereich auf Basis eines gedächtnislosen, Polynom-Modells zu regenerieren. Ein adaptives Filter passt dabei den Betrag der nichtlinearen Referenzverzerrungen an und subtrahiert diese vom verzerrten Signal. In der Arbeit wird eine Hardwareimplementierung eines Störungsminderungsalgorithmus auf einer typischen SDR Plattform vorgestellt. Bisher ist keine Implementierung des rein-digitalen Ansatzes bekannt. Der Implementierungsablauf beschreibt anhand eines Top-Bottom-Ansatzes, wie der Algorithmus zuerst in einer Festpunkt High-Level Realisierung und schließlich in einer Low-Level Implementierung mit einer Hardwarebeschreibungssprache umgesetzt wird. Sowohl High-Level als auch Low-Level Simulationen unterstützen dabei die Validierung und Bewertung der Implementierung. Die Implementierung des Abschwächungsalgorithmus stellt schließlich eine ausgefeilte Methode dar, um ein heruntergeschmischtes Basisbandspektrum in Echtzeit von nichtlinearen Verzerrungen zu befreien. Demzufolge wird die effektive Linearität des HF-Frontends erhöht. Dies kann zu einer erheblichen Verbesserung der Bitfehlerrate von modulierten Signalen führen sowie die Zuverlässigkeit des Sensings in Bezug auf kognitiven Funk steigern.Ilmenau, Techn. Univ., Masterarbeit, 201

Integrated Self-Interference Cancellation for Full-Duplex and Frequency-Division Duplexing Wireless Communication Systems

From wirelessly connected robots to car-to-car communications, and to smart cities, almost every aspect of our lives will benefit from future wireless communications. While promise an exciting future world, next-generation wireless communications impose requirements on the data rate, spectral efficiency, and latency (among others) that are higher than those for today's systems by several orders of magnitude. Full-duplex wireless, an emergent wireless communications paradigm, breaks the long-held assumption that it is impossible for a wireless device to transmit and receive simultaneously at the same frequency, and has the potential to immediately double network capacity at the physical (PHY) layer and offers many other benefits (such as reduced latency) at the higher layers. Recently, discrete-component-based demonstrations have established the feasibility of full-duplex wireless. However, the realization of integrated full duplex radios, compact radios that can fit into smartphones, is fraught with fundamental challenges. In addition, to unleash the full potential of full-duplex communication, a careful redesign of the PHY layer and the medium access control (MAC) layer using a cross-layer approach is required. The biggest challenge associated with full duplex wireless is the tremendous amount of transmitter self-interference right on top of the desired signal. In this dissertation, new self-interference-cancellation approaches at both system and circuit levels are presented, contributing towards the realization of full-duplex radios using integrated circuit technology. Specifically, these new approaches involve elimination of the noise and distortion of the cancellation circuitry, enhancing the integrated cancellation bandwidth, and performing joint radio frequency, analog, and digital cancellation to achieve cancellation with nearly one part-per-billion accuracy. In collaboration with researchers at higher layers of the stack, a cross-layer approach has been used in our full-duplex research and has allowed us to derive power allocation algorithms and to characterize rate-gain improvements for full-duplex wireless networks. To enable experimental characterization of full-duplex MAC layer algorithms, a cross-layered software-defined full-duplex radio testbed has been developed. In collaboration with researchers from the field of micro-electro-mechanical systems, we demonstrate a multi-band frequency-division duplexing system using a cavity-filter-based tunable duplexer and our integrated widely-tunable self-interference-cancelling receiver

Nonlinear Distortion in Wideband Radio Receivers and Analog-to-Digital Converters: Modeling and Digital Suppression

Emerging wireless communications systems aim to flexible and efficient usage of radio spectrum in order to increase data rates. The ultimate goal in this field is a cognitive radio. It employs spectrum sensing in order to locate spatially and temporally vacant spectrum chunks that can be used for communications. In order to achieve that, flexible and reconfigurable transceivers are needed. A software-defined radio can provide these features by having a highly-integrated wideband transceiver with minimum analog components and mostly relying on digital signal processing. This is also desired from size, cost, and power consumption point of view. However, several challenges arise, from which dynamic range is one of the most important. This is especially true on receiver side where several signals can be received simultaneously through a single receiver chain. In extreme cases the weakest signal can be almost 100 dB weaker than the strongest one. Due to the limited dynamic range of the receiver, the strongest signals may cause nonlinear distortion which deteriorates spectrum sensing capabilities and also reception of the weakest signals. The nonlinearities are stemming from the analog receiver components and also from analog-to-digital converters (ADCs). This is a performance bottleneck in many wideband communications and also radar receivers. The dynamic range challenges are already encountered in current devices, such as in wideband multi-operator receiver scenarios in mobile networks, and the challenges will have even more essential role in the future.This thesis focuses on aforementioned receiver scenarios and contributes to modeling and digital suppression of nonlinear distortion. A behavioral model for direct-conversion receiver nonlinearities is derived and it jointly takes into account RF, mixer, and baseband nonlinearities together with I/Q imbalance. The model is then exploited in suppression of receiver nonlinearities. The considered method is based on adaptive digital post-processing and does not require any analog hardware modification. It is able to extract all the necessary information directly from the received waveform in order to suppress the nonlinear distortion caused by the strongest blocker signals inside the reception band.In addition, the nonlinearities of ADCs are considered. Even if the dynamic range of the analog receiver components is not limiting the performance, ADCs may cause considerable amount of nonlinear distortion. It can originate, e.g., from undeliberate variations of quantization levels. Furthermore, the received waveform may exceed the nominal voltage range of the ADC due to signal power variations. This causes unintentional signal clipping which creates severe nonlinear distortion. In this thesis, a Fourier series based model is derived for the signal clipping caused by ADCs. Furthermore, four different methods are considered for suppressing ADC nonlinearities, especially unintentional signal clipping. The methods exploit polynomial modeling, interpolation, or symbol decisions for suppressing the distortion. The common factor is that all the methods are based on digital post-processing and are able to continuously adapt to variations in the received waveform and in the receiver itself. This is a very important aspect in wideband receivers, especially in cognitive radios, when the flexibility and state-of-the-art performance is required

Radiofrequency architectures and technologies for software defined radio

Six-port network is an interesting radiofrequency architecture with multiple possibilities. Since it was firstly introduced in the seventies as an alternative network analyzer, the six-port network has been used for many applications, such as homodyne receivers, radar systems, direction of arrival estimation, UWB (Ultra-Wide-Band), or MIMO (Multiple Input Multiple Output) systems. Currently, it is considered as a one of the best candidates to implement a Software Defined Radio (SDR). This thesis comprises an exhaustive study of this promising architecture, where its fundamentals and the state-of-the-art are also included. In addition, the design and development of a SDR 0.3-6 GHz six-port receiver prototype is presented in this thesis, which is implemented in conventional technology. The system is experimentally characterized and validated for RF signal demodulation with good performance. The analysis of the six-port architecture is complemented by a theoretical and experimental comparison with other radiofrequency architectures suitable for SDR. Some novel contributions are introduced in the present thesis. Such novelties are in the direction of the highly topical issues on six-port technique: development and optimization of real-time I-Q regeneration techniques for multiport networks; and search of new techniques and technologies to contribute to the miniaturization of the six-port architecture. In particular, the novel contributions of this thesis can be summarized as: - Introduction of a new real-time auto-calibration method for multiport receivers, particularly suitable for broadband designs and high data rate applications. - Introduction of a new direct baseband I-Q regeneration technique for five-port receivers. - Contribution to the miniaturization of six-port receivers by the use of the multilayer LTCC (Low Temperature Cofired Ceramic) technology. Implementation of a compact (30x30x1.25 mm) broadband (0.3-6 GHz) six-port receiver in LTTC technology. The results and conclusions derived from this thesis have been satisfactory, and quite fruitful in terms of publications. A total of fourteen works have been published, considering international journals and conferences, and national conferences. Aditionally, a paper has been submitted to an internationally recognized journal, which is currently under review

Calibrated Continuous-Time Sigma-Delta Modulators

To provide more information mobility, many wireless communication systems such as WCDMA and EDGE in phone systems, bluetooth and WIMAX in communication networks have been recently developed. Recent efforts have been made to build the allin- one next generation device which integrates a large number of wireless services into a single receiving path in order to raise the competitiveness of the device. Among all the receiver architectures, the high-IF receiver presents several unique properties for the next generation receiver by digitalizing the signal at the intermediate frequency around a few hundred MHz. In this architecture, the modulation/demodulation schemes, protocols, equalization, etc., are all determined in a software platform that runs in the digital signal processor (DSP) or FPGA. The specifications for most of front-end building blocks are relaxed, except the analog-to-digital converter (ADC). The requirements of large bandwidth, high operational frequency and high resolution make the design of the ADC very challenging. Solving the bottleneck associated with the high-IF receiver architecture is a major focus of many ongoing research efforts. In this work, a 6th-order bandpass continuous time sigma-delta ADC with measured 68.4dB SNDR at 10MHz bandwidth to accommodate video applications is proposed. Tuned at 200 MHz, the fs/4 architecture employs an 800 MHz clock frequency. By making use of a unique software-based calibration scheme together with the tuning properties of the bandpass filters developed under the umbrella of this project, the ADC performance is optimized automatically to fulfill all requirements for the high-IF architecture. In a separate project, other critical design issues for continuous-time sigma-delta ADCs are addressed, especially the issues related to unit current source mismatches in multi-level DACs as well as excess loop delays that may cause loop instability. The reported solutions are revisited to find more efficient architectures. The aforementioned techniques are used for the design of a 25MHz bandwidth lowpass continuous-time sigma-delta modulator with time-domain two-step 3-bit quantizer and DAC for WiMAX applications. The prototype is designed by employing a level-to-pulse-width modulation (PWM) converter followed by a single-level DAC in the feedback path to translate the typical digital codes into PWM signals with the proposed pulse arrangement. Therefore, the non-linearity issue from current source mismatch in multi-level DACs is prevented. The jitter behavior and timing mismatch issue of the proposed time-based methods are fully analyzed. The measurement results of a chip prototype achieving 67.7dB peak SNDR and 78dB SFDR in 25MHz bandwidth properly demonstrate the design concepts and effectiveness of time-based quantization and feedback. Both continuous-time sigma-delta ADCs were fabricated in mainstream CMOS 0.18um technologies, which are the most popular in today?s consumer electronics industry