HIGH PERFORMANCE, LOW COST SUBSPACE DECOMPOSITION AND POLYNOMIAL ROOTING FOR REAL TIME DIRECTION OF ARRIVAL ESTIMATION: ANALYSIS AND IMPLEMENTATION

This thesis develops high performance real-time signal processing modules for direction of arrival (DOA) estimation for localization systems. It proposes highly parallel algorithms for performing subspace decomposition and polynomial rooting, which are otherwise traditionally implemented using sequential algorithms. The proposed algorithms address the emerging need for real-time localization for a wide range of applications. As the antenna array size increases, the complexity of signal processing algorithms increases, making it increasingly difficult to satisfy the real-time constraints. This thesis addresses real-time implementation by proposing parallel algorithms, that maintain considerable improvement over traditional algorithms, especially for systems with larger number of antenna array elements. Singular value decomposition (SVD) and polynomial rooting are two computationally complex steps and act as the bottleneck to achieving real-time performance. The proposed algorithms are suitable for implementation on field programmable gated arrays (FPGAs), single instruction multiple data (SIMD) hardware or application specific integrated chips (ASICs), which offer large number of processing elements that can be exploited for parallel processing. The designs proposed in this thesis are modular, easily expandable and easy to implement. Firstly, this thesis proposes a fast converging SVD algorithm. The proposed method reduces the number of iterations it takes to converge to correct singular values, thus achieving closer to real-time performance. A general algorithm and a modular system design are provided making it easy for designers to replicate and extend the design to larger matrix sizes. Moreover, the method is highly parallel, which can be exploited in various hardware platforms mentioned earlier. A fixed point implementation of proposed SVD algorithm is presented. The FPGA design is pipelined to the maximum extent to increase the maximum achievable frequency of operation. The system was developed with the objective of achieving high throughput. Various modern cores available in FPGAs were used to maximize the performance and details of these modules are presented in detail. Finally, a parallel polynomial rooting technique based on Newton’s method applicable exclusively to root-MUSIC polynomials is proposed. Unique characteristics of root-MUSIC polynomial’s complex dynamics were exploited to derive this polynomial rooting method. The technique exhibits parallelism and converges to the desired root within fixed number of iterations, making this suitable for polynomial rooting of large degree polynomials. We believe this is the first time that complex dynamics of root-MUSIC polynomial were analyzed to propose an algorithm. In all, the thesis addresses two major bottlenecks in a direction of arrival estimation system, by providing simple, high throughput, parallel algorithms

Digital Signal Processor Based Real-Time Phased Array Radar Backend System and Optimization Algorithms

This dissertation presents an implementation of multifunctional large-scale phased array radar based on the scalable DSP platform. The challenge of building large-scale phased array radar backend is how to address the compute-intensive operations and high data throughput requirement in both front-end and backend in real-time. In most of the applications, FPGA or VLSI hardware are typically used to solve those difficulties. However, with the help of the fast development of IC industry, using a parallel set of high-performing programmable chips can be an alternative. We present a hybrid high-performance backend system by using DSP as the core computing device and MTCA as the system frame. Thus, the mapping techniques for the front and backend signal processing algorithm based on DSP are discussed in depth. Beside high-efficiency computing device, the system architecture would be a major factor influencing the reliability and performance of the backend system. The reliability requires the system must incorporate the redundancy both in hardware and software. In this dissertation, we propose a parallel modular system based on MTCA chassis, which can be reliable, scalable, and fault-tolerant. Finally, we present an example of high performance phased array radar backend, in which there is the number of 220 DSPs, achieving 7000 GFLOPS calculation from 768 channels. This example shows the potential of using the combination of DSP and MTCA as the computing platform for the future multi-functional large-scale phased array radar

GNSS array-based acquisition: theory and implementation

This Dissertation addresses the signal acquisition problem using antenna arrays in the general framework of Global Navigation Satellite Systems (GNSS) receivers. The term GNSS classi es those navigation systems based on a constellation of satellites, which emit ranging signals useful for positioning. Although the American GPS is already available, which coexists with the renewed Russian Glonass, the forthcoming European contribution (Galileo) along with the Chinese Compass will be operative soon. Therefore, a variety of satellite constellations and signals will be available in the next years. GNSSs provide the necessary infrastructures for a myriad of applications and services that demand a robust and accurate positioning service. The positioning availability must be guaranteed all the time, specially in safety-critical and mission-critical services. Examining the threats against the service availability, it is important to take into account that all the present and the forthcoming GNSSs make use of Code Division Multiple Access (CDMA) techniques. The ranging signals are received with very low precorrelation signal-to-noise ratio (in the order of ���22 dB for a receiver operating at the Earth surface). Despite that the GNSS CDMA processing gain o ers limited protection against Radio Frequency interferences (RFI), an interference with a interference-to-signal power ratio that exceeds the processing gain can easily degrade receivers' performance or even deny completely the GNSS service, specially conventional receivers equipped with minimal or basic level of protection towards RFIs. As a consequence, RFIs (either intentional or unintentional) remain as the most important cause of performance degradation. A growing concern of this problem has appeared in recent times. Focusing our attention on the GNSS receiver, it is known that signal acquisition has the lowest sensitivity of the whole receiver operation, and, consequently, it becomes the performance bottleneck in the presence of interfering signals. A single-antenna receiver can make use of time and frequency diversity to mitigate interferences, even though the performance of these techniques is compromised in low SNR scenarios or in the presence of wideband interferences. On the other hand, antenna arrays receivers can bene t from spatial-domain processing, and thus mitigate the e ects of interfering signals. Spatial diversity has been traditionally applied to the signal tracking operation of GNSS receivers. However, initial tracking conditions depend on signal acquisition, and there are a number of scenarios in which the acquisition process can fail as stated before. Surprisingly, to the best of our knowledge, the application of antenna arrays to GNSS signal acquisition has not received much attention. This Thesis pursues a twofold objective: on the one hand, it proposes novel arraybased acquisition algorithms using a well-established statistical detection theory framework, and on the other hand demonstrates both their real-time implementation feasibility and their performance in realistic scenarios. The Dissertation starts with a brief introduction to GNSS receivers fundamentals, providing some details about the navigation signals structure and the receiver's architecture of both GPS and Galileo systems. It follows with an analysis of GNSS signal acquisition as a detection problem, using the Neyman-Pearson (NP) detection theory framework and the single-antenna acquisition signal model. The NP approach is used here to derive both the optimum detector (known as clairvoyant detector ) and the sov called Generalized Likelihood Ratio Test (GLRT) detector, which is the basis of almost all of the current state-of-the-art acquisition algorithms. Going further, a novel detector test statistic intended to jointly acquire a set of GNSS satellites is obtained, thus reducing both the acquisition time and the required computational resources. The eff ects of the front-end bandwidth in the acquisition are also taken into account. Then, the GLRT is extended to the array signal model to obtain an original detector which is able to mitigate temporally uncorrelated interferences even if the array is unstructured and moderately uncalibrated, thus becoming one of the main contributions of this Dissertation. The key statistical feature is the assumption of an arbitrary and unknown covariance noise matrix, which attempts to capture the statistical behavior of the interferences and other non-desirable signals, while exploiting the spatial dimension provided by antenna arrays. Closed form expressions for the detection and false alarm probabilities are provided. Performance and interference rejection capability are modeled and compared both to their theoretical bound. The proposed array-based acquisition algorithm is also compared to conventional acquisition techniques performed after blind null-steering beamformer approaches, such as the power minimization algorithm. Furthermore, the detector is analyzed under realistic conditions, accounting for the presence of errors in the covariance matrix estimation, residual Doppler and delay errors, and signal quantization e ects. Theoretical results are supported by Monte Carlo simulations. As another main contribution of this Dissertation, the second part of the work deals with the design and the implementation of a novel Field Programmable Gate Array (FPGA)-based GNSS real-time antenna-array receiver platform. The platform is intended to be used as a research tool tightly coupled with software de ned GNSS receivers. A complete signal reception chain including the antenna array and the multichannel phase-coherent RF front-end for the GPS L1/ Galileo E1 was designed, implemented and tested. The details of the digital processing section of the platform, such as the array signal statistics extraction modules, are also provided. The design trade-o s and the implementation complexities were carefully analyzed and taken into account. As a proof-of-concept, the problem of GNSS vulnerability to interferences was addressed using the presented platform. The array-based acquisition algorithms introduced in this Dissertation were implemented and tested under realistic conditions. The performance of the algorithms were compared to single antenna acquisition techniques, measured under strong in-band interference scenarios, including narrow/wide band interferers and communication signals. The platform was designed to demonstrate the implementation feasibility of novel array-based acquisition algorithms, leaving the rest of the receiver operations (mainly, tracking, navigation message decoding, code and phase observables, and basic Position, Velocity and Time (PVT) solution) to a Software De ned Radio (SDR) receiver running in a personal computer, processing in real-time the spatially- ltered signal sample stream coming from the platform using a Gigabit Ethernet bus data link. In the last part of this Dissertation, we close the loop by designing and implementing such software receiver. The proposed software receiver targets multi-constellation/multi-frequency architectures, pursuing the goals of e ciency, modularity, interoperability, and exibility demanded by user domains that require non-standard features, such as intermediate signals or data extraction and algorithms interchangeability. In this context, we introduce an open-source, real-time GNSS software de ned receiver (so-named GNSS-SDR) that contributes with several novel features such as the use of software design patterns and shared memory techniques to manage e ciently the data ow between receiver blocks, the use of hardware-accelerated instructions for time-consuming vector operations like carrier wipe-o and code correlation, and the availability to compile and run on multiple software platforms and hardware architectures. At this time of writing (April 2012), the receiver enjoys of a 2-dimensional Distance Root Mean Square (DRMS) error lower than 2 meters for a GPS L1 C/A scenario with 8 satellites in lock and a Horizontal Dilution Of Precision (HDOP) of 1.2.Esta tesis aborda el problema de la adquisición de la señal usando arrays de antenas en el marco general de los receptores de Sistemas Globales de Navegación por Satélite (GNSS). El término GNSS engloba aquellos sistemas de navegación basados en una constelación de satélites que emiten señales útiles para el posicionamiento. Aunque el GPS americano ya está disponible, coexistiendo con el renovado sistema ruso GLONASS, actualmente se está realizando un gran esfuerzo para que la contribución europea (Galileo), junto con el nuevo sistema chino Compass, estén operativos en breve. Por lo tanto, una gran variedad de constelaciones de satélites y señales estarán disponibles en los próximos años. Estos sistemas proporcionan las infraestructuras necesarias para una multitud de aplicaciones y servicios que demandan un servicio de posicionamiento confiable y preciso. La disponibilidad de posicionamiento se debe garantizar en todo momento, especialmente en los servicios críticos para la seguridad de las personas y los bienes. Cuando examinamos las amenazas de la disponibilidad del servicio que ofrecen los GNSSs, es importante tener en cuenta que todos los sistemas presentes y los sistemas futuros ya planificados hacen uso de técnicas de multiplexación por división de código (CDMA). Las señales transmitidas por los satélites son recibidas con una relación señal-ruido (SNR) muy baja, medida antes de la correlación (del orden de -22 dB para un receptor ubicado en la superficie de la tierra). A pesar de que la ganancia de procesado CDMA ofrece una protección inherente contra las interferencias de radiofrecuencia (RFI), esta protección es limitada. Una interferencia con una relación de potencia de interferencia a potencia de la señal que excede la ganancia de procesado puede degradar el rendimiento de los receptores o incluso negar por completo el servicio GNSS. Este riesgo es especialmente importante en receptores convencionales equipados con un nivel mínimo o básico de protección frente las RFIs. Como consecuencia, las RFIs (ya sean intencionadas o no intencionadas), se identifican como la causa más importante de la degradación del rendimiento en GNSS. El problema esta causando una preocupación creciente en los últimos tiempos, ya que cada vez hay más servicios que dependen de los GNSSs Si centramos la atención en el receptor GNSS, es conocido que la adquisición de la señal tiene la menor sensibilidad de todas las operaciones del receptor, y, en consecuencia, se convierte en el factor limitador en la presencia de señales interferentes. Un receptor de una sola antena puede hacer uso de la diversidad en tiempo y frecuencia para mitigar las interferencias, aunque el rendimiento de estas técnicas se ve comprometido en escenarios con baja SNR o en presencia de interferencias de banda ancha. Por otro lado, los receptores basados en múltiples antenas se pueden beneficiar del procesado espacial, y por lo tanto mitigar los efectos de las señales interferentes. La diversidad espacial se ha aplicado tradicionalmente a la operación de tracking de la señal en receptores GNSS. Sin embargo, las condiciones iniciales del tracking dependen del resultado de la adquisición de la señal, y como hemos visto antes, hay un número de situaciones en las que el proceso de adquisición puede fallar. En base a nuestro grado de conocimiento, la aplicación de los arrays de antenas a la adquisición de la señal GNSS no ha recibido mucha atención, sorprendentemente. El objetivo de esta tesis doctoral es doble: por un lado, proponer nuevos algoritmos para la adquisición basados en arrays de antenas, usando como marco la teoría de la detección de señal estadística, y por otro lado, demostrar la viabilidad de su implementación y ejecución en tiempo real, así como su medir su rendimiento en escenarios realistas. La tesis comienza con una breve introducción a los fundamentos de los receptores GNSS, proporcionando algunos detalles sobre la estructura de las señales de navegación y la arquitectura del receptor aplicada a los sistemas GPS y Galileo. Continua con el análisis de la adquisición GNSS como un problema de detección, aplicando la teoría del detector Neyman-Pearson (NP) y el modelo de señal de una única antena. El marco teórico del detector NP se utiliza aquí para derivar tanto el detector óptimo (conocido como detector clarividente) como la denominada Prueba Generalizada de la Razón de Verosimilitud (en inglés, Generalized Likelihood Ratio Test (GLRT)), que forma la base de prácticamente todos los algoritmos de adquisición del estado del arte actual. Yendo más lejos, proponemos un nuevo detector diseñado para adquirir simultáneamente un conjunto de satélites, por lo tanto, obtiene una reducción del tiempo de adquisición y de los recursos computacionales necesarios en el proceso, respecto a las técnicas convencionales. El efecto del ancho de banda del receptor también se ha tenido en cuenta en los análisis. A continuación, el detector GLRT se extiende al modelo de señal de array de antenas para obtener un detector nuevo que es capaz de mitigar interferencias no correladas temporalmente, incluso utilizando arrays no estructurados y moderadamente descalibrados, convirtiéndose así en una de las principales aportaciones de esta tesis. La clave del detector es asumir una matriz de covarianza de ruido arbitraria y desconocida en el modelo de señal, que trata de captar el comportamiento estadístico de las interferencias y otras señales no deseadas, mientras que utiliza la dimensión espacial proporcionada por los arrays de antenas. Se han derivado las expresiones que modelan las probabilidades teóricas de detección y falsa alarma. El rendimiento del detector y su capacidad de rechazo a interferencias se han modelado y comparado con su límite teórico. El algoritmo propuesto también ha sido comparado con técnicas de adquisición convencionales, ejecutadas utilizando la salida de conformadores de haz que utilizan algoritmos de filtrado de interferencias, como el algoritmo de minimización de la potencia. Además, el detector se ha analizado bajo condiciones realistas, representadas con la presencia de errores en la estimación de covarianzas, errores residuales en la estimación del Doppler y el retardo de señal, y los efectos de la cuantificación. Los resultados teóricos se apoyan en simulaciones de Monte Carlo. Como otra contribución principal de esta tesis, la segunda parte del trabajo trata sobre el diseño y la implementación de una nueva plataforma para receptores GNSS en tiempo real basados en array de antenas que utiliza la tecnología de matriz programable de puertas lógicas (en ingles Field Programmable Gate Array (FPGA)). La plataforma está destinada a ser utilizada como una herramienta de investigación estrechamente acoplada con receptores GNSS definidos por software. Se ha diseñado, implementado y verificado la cadena completa de recepción, incluyendo el array de antenas y el front-end multi-canal para las señales GPS L1 y Galileo E1. El documento explica en detalle el procesado de señal que se realiza, como por ejemplo, la implementación del módulo de extracción de estadísticas de la señal. Los compromisos de diseño y las complejidades derivadas han sido cuidadosamente analizadas y tenidas en cuenta. La plataforma ha sido utilizada como prueba de concepto para solucionar el problema presentado de la vulnerabilidad del GNSS a las interferencias. Los algoritmos de adquisición introducidos en esta tesis se han implementado y probado en condiciones realistas. El rendimiento de los algoritmos se comparó con las técnicas de adquisición basadas en una sola antena. Se han realizado pruebas en escenarios que contienen interferencias dentro de la banda GNSS, incluyendo interferencias de banda estrecha y banda ancha y señales de comunicación. La plataforma fue diseñada para demostrar la viabilidad de la implementación de nuevos algoritmos de adquisición basados en array de antenas, dejando el resto de las operaciones del receptor (principalmente, los módulos de tracking, decodificación del mensaje de navegación, los observables de código y fase, y la solución básica de Posición, Velocidad y Tiempo (PVT)) a un receptor basado en el concepto de Radio Definida por Software (SDR), el cual se ejecuta en un ordenador personal. El receptor procesa en tiempo real las muestras de la señal filltradas espacialmente, transmitidas usando el bus de datos Gigabit Ethernet. En la última parte de esta Tesis, cerramos ciclo diseñando e implementando completamente este receptor basado en software. El receptor propuesto está dirigido a las arquitecturas de multi-constalación GNSS y multi-frecuencia, persiguiendo los objetivos de eficiencia, modularidad, interoperabilidad y flexibilidad demandada por los usuarios que requieren características no estándar, tales como la extracción de señales intermedias o de datos y intercambio de algoritmos. En este contexto, se presenta un receptor de código abierto que puede trabajar en tiempo real, llamado GNSS-SDR, que contribuye con varias características nuevas. Entre ellas destacan el uso de patrones de diseño de software y técnicas de memoria compartida para administrar de manera eficiente el uso de datos entre los bloques del receptor, el uso de la aceleración por hardware para las operaciones vectoriales más costosas, como la eliminación de la frecuencia Doppler y la correlación de código, y la disponibilidad para compilar y ejecutar el receptor en múltiples plataformas de software y arquitecturas de hardware. A fecha de la escritura de esta Tesis (abril de 2012), el receptor obtiene un rendimiento basado en la medida de la raíz cuadrada del error cuadrático medio en la distancia bidimensional (en inglés, 2-dimensional Distance Root Mean Square (DRMS) error) menor de 2 metros para un escenario GPS L1 C/A con 8 satélites visibles y una dilución de la precisión horizontal (en inglés, Horizontal Dilution Of Precision (HDOP)) de 1.2

Two-dimensional direction-of-arrival estimation with time-modulated arrays

Two-dimensional direction-of-arrival estimation with time-modulated array

Acceleration Techniques for Sparse Recovery Based Plane-wave Decomposition of a Sound Field

Plane-wave decomposition by sparse recovery is a reliable and accurate technique for plane-wave decomposition which can be used for source localization, beamforming, etc. In this work, we introduce techniques to accelerate the plane-wave decomposition by sparse recovery. The method consists of two main algorithms which are spherical Fourier transformation (SFT) and sparse recovery. Comparing the two algorithms, the sparse recovery is the most computationally intensive. We implement the SFT on an FPGA and the sparse recovery on a multithreaded computing platform. Then the multithreaded computing platform could be fully utilized for the sparse recovery. On the other hand, implementing the SFT on an FPGA helps to flexibly integrate the microphones and improve the portability of the microphone array. For implementing the SFT on an FPGA, we develop a scalable FPGA design model that enables the quick design of the SFT architecture on FPGAs. The model considers the number of microphones, the number of SFT channels and the cost of the FPGA and provides the design of a resource optimized and cost-effective FPGA architecture as the output. Then we investigate the performance of the sparse recovery algorithm executed on various multithreaded computing platforms (i.e., chip-multiprocessor, multiprocessor, GPU, manycore). Finally, we investigate the influence of modifying the dictionary size on the computational performance and the accuracy of the sparse recovery algorithms. We introduce novel sparse-recovery techniques which use non-uniform dictionaries to improve the performance of the sparse recovery on a parallel architecture

KAVUAKA: a low-power application-specific processor architecture for digital hearing aids

The power consumption of digital hearing aids is very restricted due to their small physical size and the available hardware resources for signal processing are limited. However, there is a demand for more processing performance to make future hearing aids more useful and smarter. Future hearing aids should be able to detect, localize, and recognize target speakers in complex acoustic environments to further improve the speech intelligibility of the individual hearing aid user. Computationally intensive algorithms are required for this task. To maintain acceptable battery life, the hearing aid processing architecture must be highly optimized for extremely low-power consumption and high processing performance.The integration of application-specific instruction-set processors (ASIPs) into hearing aids enables a wide range of architectural customizations to meet the stringent power consumption and performance requirements. In this thesis, the application-specific hearing aid processor KAVUAKA is presented, which is customized and optimized with state-of-the-art hearing aid algorithms such as speaker localization, noise reduction, beamforming algorithms, and speech recognition. Specialized and application-specific instructions are designed and added to the baseline instruction set architecture (ISA). Among the major contributions are a multiply-accumulate (MAC) unit for real- and complex-valued numbers, architectures for power reduction during register accesses, co-processors and a low-latency audio interface. With the proposed MAC architecture, the KAVUAKA processor requires 16 % less cycles for the computation of a 128-point fast Fourier transform (FFT) compared to related programmable digital signal processors. The power consumption during register file accesses is decreased by 6 %to 17 % with isolation and by-pass techniques. The hardware-induced audio latency is 34 %lower compared to related audio interfaces for frame size of 64 samples.The final hearing aid system-on-chip (SoC) with four KAVUAKA processor cores and ten co-processors is integrated as an application-specific integrated circuit (ASIC) using a 40 nm low-power technology. The die size is 3.6 mm2. Each of the processors and co-processors contains individual customizations and hardware features with a varying datapath width between 24-bit to 64-bit. The core area of the 64-bit processor configuration is 0.134 mm2. The processors are organized in two clusters that share memory, an audio interface, co-processors and serial interfaces. The average power consumption at a clock speed of 10 MHz is 2.4 mW for SoC and 0.6 mW for the 64-bit processor.Case studies with four reference hearing aid algorithms are used to present and evaluate the proposed hardware architectures and optimizations. The program code for each processor and co-processor is generated and optimized with evolutionary algorithms for operation merging,instruction scheduling and register allocation. The KAVUAKA processor architecture is com-pared to related processor architectures in terms of processing performance, average power consumption, and silicon area requirements

A tutorial on the characterisation and modelling of low layer functional splits for flexible radio access networks in 5G and beyond

The centralization of baseband (BB) functions in a radio access network (RAN) towards data processing centres is receiving increasing interest as it enables the exploitation of resource pooling and statistical multiplexing gains among multiple cells, facilitates the introduction of collaborative techniques for different functions (e.g., interference coordination), and more efficiently handles the complex requirements of advanced features of the fifth generation (5G) new radio (NR) physical layer, such as the use of massive multiple input multiple output (MIMO). However, deciding the functional split (i.e., which BB functions are kept close to the radio units and which BB functions are centralized) embraces a trade-off between the centralization benefits and the fronthaul costs for carrying data between distributed antennas and data processing centres. Substantial research efforts have been made in standardization fora, research projects and studies to resolve this trade-off, which becomes more complicated when the choice of functional splits is dynamically achieved depending on the current conditions in the RAN. This paper presents a comprehensive tutorial on the characterisation, modelling and assessment of functional splits in a flexible RAN to establish a solid basis for the future development of algorithmic solutions of dynamic functional split optimisation in 5G and beyond systems. First, the paper explores the functional split approaches considered by different industrial fora, analysing their equivalences and differences in terminology. Second, the paper presents a harmonized analysis of the different BB functions at the physical layer and associated algorithmic solutions presented in the literature, assessing both the computational complexity and the associated performance. Based on this analysis, the paper presents a model for assessing the computational requirements and fronthaul bandwidth requirements of different functional splits. Last, the model is used to derive illustrative results that identify the major trade-offs that arise when selecting a functional split and the key elements that impact the requirements.This work has been partially funded by Huawei Technologies. Work by X. Gelabert and B. Klaiqi is partially funded by the European Union's Horizon Europe research and innovation programme (HORIZON-MSCA-2021-DN-0) under the Marie Skłodowska-Curie grant agreement No 101073265. Work by J. Perez-Romero and O. Sallent is also partially funded by the Smart Networks and Services Joint Undertaking (SNS JU) under the European Union’s Horizon Europe research and innovation programme under Grant Agreements No. 101096034 (VERGE project) and No. 101097083 (BeGREEN project) and by the Spanish Ministry of Science and Innovation MCIN/AEI/10.13039/501100011033 under ARTIST project (ref. PID2020-115104RB-I00). This last project has also funded the work by D. Campoy.Peer ReviewedPostprint (author's final draft

Survey of FPGA applications in the period 2000 – 2015 (Technical Report)

Romoth J, Porrmann M, Rückert U. Survey of FPGA applications in the period 2000 – 2015 (Technical Report).; 2017.Since their introduction, FPGAs can be seen in more and more different fields of applications. The key advantage is the combination of software-like flexibility with the performance otherwise common to hardware. Nevertheless, every application field introduces special requirements to the used computational architecture. This paper provides an overview of the different topics FPGAs have been used for in the last 15 years of research and why they have been chosen over other processing units like e.g. CPUs