Development of FEB Configuration Test Board for ATLAS NSW Upgrade

The FEB(front end board) configuration test board is developed aiming at meeting the requirement of testing the new generation ASIC(application-specific integrated circuit) chips and its configuration system for ATLAS NSW(New Small Wheel) upgrade, In this paper, some functions are developed in terms of the configurations of the key chips on the FEB, VMM3 and TDS2 using GBT-SCA. Additionally, a flexible communication protocol is designed, verifying the whole data link. It provides technical reference for prototype FEB key chip configuration and data readout, as well as the final system configuration

PARISROC, a Photomultiplier Array Integrated Read Out Chip

PARISROC is a complete read out chip, in AMS SiGe 0.35 !m technology, for photomultipliers array. It allows triggerless acquisition for next generation neutrino experiments and it belongs to an R&D program funded by the French national agency for research (ANR) called PMm2: ?Innovative electronics for photodetectors array used in High Energy Physics and Astroparticles? (ref.ANR-06-BLAN-0186). The ASIC (Application Specific Integrated Circuit) integrates 16 independent and auto triggered channels with variable gain and provides charge and time measurement by a Wilkinson ADC (Analog to Digital Converter) and a 24-bit Counter. The charge measurement should be performed from 1 up to 300 photo- electrons (p.e.) with a good linearity. The time measurement allowed to a coarse time with a 24-bit counter at 10 MHz and a fine time on a 100ns ramp to achieve a resolution of 1 ns. The ASIC sends out only the relevant data through network cables to the central data storage. This paper describes the front-end electronics ASIC called PARISROC.Comment: IEEE Nuclear Science Symposium an Medical Imaging Conference (2009 NSS/MIC

Proposal, development and test of an analog front-end electronic board for Nemo telescope

The NEMO collaboration is involved in the R&D of the main technologies for the project of a km3 scale underwater neutrino telescope. The proposed detector is made up of thousands of Optical Modules (hereafter OM), spread over the entire volume for Cˇ erenkov light detection. Each OMis equipped with a photo multiplier tube (PMT) and an electronic circuit for data acquisition and transmission (DAQ-Board). This work points out the possible benefits of a hybrid solution based on an analog ASIC (Application Specific Integrated Circuit) employed for the analog signal acquisition and an FPGA (Field Programmable Gate Array), a digital programmable IC (Integrated Circuit) which performs the data acquisition and the data transmission

Performance of a Low Noise Front-end ASIC for Si/CdTe Detectors in Compton Gamma-ray Telescope

Compton telescopes based on semiconductor technologies are being developed to explore the gamma-ray universe in an energy band 0.1--20 MeV, which is not well covered by the present or near-future gamma-ray telescopes. The key feature of such Compton telescopes is the high energy resolution that is crucial for high angular resolution and high background rejection capability. The energy resolution around 1 keV is required to approach physical limit of the angular resolution due to Doppler broadening. We have developed a low noise front-end ASIC (Application-Specific Integrated Circuit), VA32TA, to realize this goal for the readout of Double-sided Silicon Strip Detector (DSSD) and Cadmium Telluride (CdTe) pixel detector which are essential elements of the semiconductor Compton telescope. We report on the design and test results of the VA32TA. We have reached an energy resolution of 1.3 keV (FWHM) for 60 keV and 122 keV at 0 degree C with a DSSD and 1.7 keV (FWHM) with a CdTe detector.Comment: 6 pages, 7 figures, IEEE style file, to appear in IEEE Trans. Nucl. Sc

Front-end multi-channel PMT-associated readout chip for hodoscope application

International audienceThe system development requires a dedicated multi-channel readout ASIC (Application Specific Integrated Circuit) to be associated with the MaPMTs. Each channel should have very low input impedance to avoid electrical crosstalk between adjacent channels and to minimize effects of detector and wiring capacitances (Cd + Cw). Crosstalk between channels may degrade position resolution, while these capacitances may degrade both frequency and noise performances. Each channel should also provide two separated outputs corresponding respectively to high-speed signal-event detection and low-noise signal-charge quantification at low counting rate. This paper presents a readout chip for this purpose. It has been designed in a 0.35µm SiGe BiCMOS process (AMS). This process allows the use of RF and large-transconductance bipolar components, which is useful for the design of wide-band, low-impedance and low-noise circuits with improved performances

Chip Design by means of Application Specific Integrated Circuit and Operational test using Automated Test Equipment

"In recently, hardware description language (HDL) is the most powerful tools for the design and development of Large Integrate Circuit (LSI). LSI circuit using ASIC (Application Specific Integrated Circuit) technology has advantages for such as low consumption and short processing time. In this paper, we have reported that the LSI circuit using ASIC technology is designed and verified for simple operation. In this paper describes the more detail operation verification in our circuit by means of an Automated Test Equipment. As a result, we can demonstrate the difference in maximum operational frequency under different the layout designs.

Chip Design by means of Application Specific Integrated Circuit and Operational test using Automated Test Equipment

"In recently, hardware description language (HDL) is the most powerful tools for the design and development of Large Integrate Circuit (LSI). LSI circuit using ASIC (Application Specific Integrated Circuit) technology has advantages for such as low consumption and short processing time. In this paper, we have reported that the LSI circuit using ASIC technology is designed and verified for simple operation. In this paper describes the more detail operation verification in our circuit by means of an Automated Test Equipment. As a result, we can demonstrate the difference in maximum operational frequency under different the layout designs.

High level behavioural modelling of boundary scan architecture.

This project involves the development of a software tool which enables the integration of the IEEE 1149.1/JTAG Boundary Scan Test Architecture automatically into an ASIC (Application Specific Integrated Circuit) design. The tool requires the original design (the ASIC) to be described in VHDL-IEEE 1076 Hardware Description Language. The tool consists of the two major elements: i) A parsing and insertion algorithm developed and implemented in 'C'; ii) A high level model of the Boundary Scan Test Architecture implemented in 'VHDL'. The parsing and insertion algorithm is developed to deal with identifying the design Input/Output (I/O) terminals, their types and the order they appear in the ASIC design. It then attaches suitable Boundary Scan Cells to each I/O, except power and ground and inserts the high level models of the full Boundary Scan Architecture into the ASIC without altering the design core structure