Using an FPGA for Fast Bit Accurate SoC Simulation

In this paper we describe a sequential simulation method to simulate large parallel homo- and heterogeneous systems on a single FPGA. The method is applicable for parallel systems were lengthy cycle and bit accurate simulations are required. It is particularly designed for systems that do not fit completely on the simulation platform (i.e. FPGA). As a case study, we use a Network-on-Chip (NoC) that is simulated in SystemC and on the described FPGA simulator. This enables us to observe the NoC behavior under a large variety of traffic patterns. Compared with the SystemC simulation we achieved a factor 80-300 of speed improvement, without compromising the cycle and bit level accuracy

Використання структур сучасних комп’ютерних систем для реалізації систем обробки знань

У зв’язку зі стрімким розвитком технологій програмованих логічних інтегральних схем розробка нових, більш продуктивних архітектур комп’ютерів для обробки знань залишається актуальною задачею. В роботі виконано аналіз архітектур проблемно-орієнтованих систем, а також універсальних систем. Розглянуто переваги та шляхи використання комп’ютерів із універсальною архітектурою для реалізації систем обробки знань.В связи со стремительным ростом технологий программируемых логических инте- гральных схем разработка новых, более производительных архитектур компьютеров для обработки знаний остается актуальной задачей. В работе выполнен анализ архитектур проблемноориентированных и универсальных компьютерных систем. Рассмотрены преимущества и пути использования компьютеров с универсальной архитектурой для реализации систем обработки знаний.Due to the rapid technologies growth of programmable logic integrated circuits, developing of a new computer’s architectures, which effectively support knowledge processing systems, remains a relevant problem. The analysis of task-oriented architectures and universal computer systems was conducted. The advantages and ways of using computers with a universal architecture for knowledge-processing systems implementation were considered

Closing the Gap in RFC 7748: Implementing Curve448 in Hardware

With the evidence on comprised cryptographic standards in the context of elliptic curves, the IETF TLS working group has issued a request to the IETF Crypto Forum Research Group (CFRG) to recommend new elliptic curves that do not leave a doubt regarding their rigidity or any backdoors. This initiative has recently published RFC 7748 proposing two elliptic curves, known as Curve25519 and Curve448, for use with the next generation of TLS. This choice of elliptic curves was already picked up by the IETF working group curdle for adoption in further security protocols, such as DNSSEC. Hence it can be expected that these two curves will become predominant in the Internet and will form one basis for future secure communication. Unfortunately, both curves were solely designed and optimized for pure software implementation; their implementation in hardware or their physical protection against side-channel attacks were not considered at any time. However, for Curve25519 it has been shown recently that efficient implementations in hardware along with side-channel protection are possible. In this work we aim to close this gap and demonstrate that fortunately the second curve can be efficiently implemented in hardware as well. More precisely, we demonstrate that the high-security Curve448 can be implemented on a Xilinx XC7Z7020 at moderate costs of just 963 logic and 30 DSP slices and performs a scalar multiplication in 2.5ms

On Demand Nanoscale Phase Manipulation of Vanadium Dioxide by Scanning Probe Lithography

This dissertation focuses on nanoscale phase manipulations of Vanadium Dioxide. Nanoscale control of material properties is a current obstacle for the next generation of optoelectronic and photonic devices. Vanadium Dioxide is a strongly correlated material with an insulator-metal phase transition at approximately 345 K that generates dramatic electronic and optical property changes. However, the development of industry device application based on this phenomenon has been limited thus far due to the macroscopic scale and the volatile nature of the phase transition. In this work these limitations are assessed and circumvented. A home-built, variable temperature, scanning near-field optical microscope was engineered for Vanadium Dioxide manipulations and detections. Using this instrument, various scanning probe lithography based methods are implemented to induce new nanoscale phases. Three new phase transitions are discovered; a monoclinic metallic at the nanoscale, a rutile metallic metastable phase, and a van der Waals layered insulator. These new phases are studied and characterized to further understand phase manipulations in strongly correlated materials. One of the new phase transitions, monoclinic metallic, showcases plasmonic excitations. This phenomenon is used to demonstrate various nanoplasmonic devices such as rewritable waveguides, spatially modulated resonators, and reconfigurable planar optics. Finally, Oxygen Vacancy diffusion of the monoclinic structure is monitored to determine the temporal limitation for device applications. The discovery, demonstration, and study of these phases clearly shows the ability to manipulate Vanadium Dioxide on the nanoscale for the first time. Phase control is accomplished under ambient conditions and is stable over long periods of time. This technology opens the door for multifunctional device application using strongly correlated materials

The automated compilation of comprehensive hardware design search spaces of algorithmic-based implementations for FPGA design exploration

Over the past few years FPGA hardware has become a logical choice for implementing cutting-edge signal processing applications. While there have been advances in FPGA technology, the common process of creating specialized hardware implementations for them is a manual one involving extensive design exploration. Design exploration is a process that requires a designer to look for designs that ¯t a set of performance characteristics such as size, throughput, or power depending on the application and it can be the most time consuming step when creating FPGA hardware. This process is a nontrivial task that requires extensive background knowledgeof both FPGA hardware and the application being implemented. While advances have been made in automating the process of design, there is still a gap between the application writers and hardware engineers that can be filled.This thesis presents a novel approach for automating the generation of hardware design search spaces that contain a comprehensive set of ways to implement signal processing algorithms with FPGAs. To accomplish this we generate a set of equivalent mathematical representations for an input equation via a novel declarative programming language that avoids a number of di±culties associated with the imperative languages used by previous approaches. We show that this equation space is bounded in terms of bracketing and ordering of mathematical operations, and that by changing the way an equation is written we can generate unique hardware instantiations (designs). The generated instantiations are mapped to heterogeneous computing architectures and written in a structural hardware descriptive language style to ensure that the intended instantiation will behave as predicted in hardware.A software system was created based on this approach that generates an equation space for varying numbers of summed multiplications and converts each representation into a comprehensive hardware design search space that can be analyzed for performance characteristics such as size, throughput, latency, and power.Ph.D., Electrical Engineering -- Drexel University, 200

Coprocesadores dinámicamente reconfigurables en sistemas embebidos basados en FPGAs: Tesis doctoral

Tesis doctoral inédita leída en la Universidad Autónoma de Madrid. Escuela Politécnica Superior, Departamento de Ingeniería Informática. Fecha de lectura: 12-05-2006

Evaluation of a Locomotion Algorithm for Worm-Like Robots on FPGA-Embedded Processors

The final publication is available at Springer via http://dx.doi.org/10.1007/11802839_4Revised Selected Papers of Second International Workshop, ARC 2006, Delft, The Netherlands, March 1-3, 2006,In this paper, a locomotion algorithm designed for an eight modules worm-like robot has been successfully tested on three different FPGA-embedded processors: MicroBlaze, PowerPC and LEON2. The locomotion of worm-like robots, composed of a chain of equal linked modules, is achieved by means of wave propagation that traverse the body of the worm. The time the robot needs to generate a new motion wave, also known as the gait recalculation time, is the key to achieve an autonomous robot with real-time reactions. Algorithm execution time for four different architectures, as a function of the total number of articulations of the robot, are presented. The results show that a huge improvement of the gait recalculation time can be achieved by using a float point unit. The performance achieved using the LEON2 with FPU is 40 times better than LEON2 without FPU, using only 6% of additional resources