High-Tech Urban Agriculture in Amsterdam : An Actor Network Analysis

The agriculture and horticulture sector in the Netherlands is one of the most productive in the world. Although the sector is one of the most advanced and intense agricultural production systems worldwide, it faces challenges, such as climate change and environmental and social unsustainability of industrial production. To overcome these challenges, alternative food production initiatives have emerged, especially in large cities such as Amsterdam. Some initiatives involve producing food in the urban environment, supported by new technologies and practices, so-called high-tech urban agriculture (HTUA). These initiatives make cultivation of plants inside and on top of buildings possible and increase green spaces in urban areas. The emerging agricultural technologies are creating new business environments that are shape d by technology developers (e.g., suppliers of horticultural light emitting diodes (LED) and control environment systems) and developers of alternative food production practices (e.g., HTUA start-ups). However, research shows that the uptake of these technological innovations in urban planning processes is problematic. Therefore, this research analyzes the barriers that local government planners and HTUA developers are facing in the embedding of HTUA in urban planning processes, using the city of Amsterdam as a case study. This study draws on actor-network theory (ANT) to analyze the interactions between planners, technologies, technology developers and developers of alternative food production practices. Several concepts of ANT are integrated into a multi-level perspective on sustainability transitions (MLP) to create a new theoretical framework that can explain how interactions between technologies and planning actors transform the incumbent social\u2013technical regime. The configuration of interactions between social and material entities in technology development and adoption processes in Amsterdam is analyzed through the lens of this theoretical framework. The data in this study were gathered by tracing actors and their connections by using ethnographic research methods. In the course of the integration of new technologies into urban planning practices, gaps between technologies, technology developers, and planning actors have been identified. The results of this study show a lacking connection between planning actors and technology developers, although planning actors do interact with developers of alternative food production practices. These interactions are influenced by agency of artefacts such as visualizations of the future projects. The paper concludes that for the utilization of emerging technologies for sustainability transition of cities, the existing gap between technology developers and planning actors needs to be bridged through the integration of technology development visions in urban agendas and planning processe

Analog and Mixed Signal Verification using Satisfiability Solver on Discretized Models

With increasing demand of performance constraints and the ever reducing size of the IC chips, analog and mixed-signal designs have become indispensable and increasingly complex in modern CMOS technologies. This has resulted in the rise of stochastic behavior in circuits, making it important to detect all the corner cases and verify the correct functionality of the design under all circumstances during the earlier stages of the design process. It can be achieved by functional or formal verification methods, which are still widely unexplored for Analog and Mixed-Signal (AMS) designs. Design Verification is a process to validate the performance of the system in accordance with desired specifications. Functional verification relies on simulating different combinations of inputs for maximum state space coverage. With the exponential increase in the complexity of circuits, traditional functional verification techniques are getting more and more inadequate in terms of exhaustiveness of the solution. Formal verification attempts to provide a mathematical proof for the correctness of the design regardless of the circumstances. Thus, it is possible to get 100% coverage using formal verification. However, it requires advanced mathematics knowledge and thus is not feasible for all applications. In this thesis, we present a technique for analog and mixed-signal verification targeting DC verification using Berkeley Short-channel Igfet Models (BSIM) for approximation. The verification problem is first defined using the state space equations for the given circuit and applying Satisfiability Modulo Theories (SMT) solver to determine a region that encloses complete DC equilibrium of the circuit. The technique is applied to an example circuit and the results are analyzed in turns of runtime effectiveness

Dependable Digitally-Assisted Mixed-Signal IPs Based on Integrated Self-Test & Self-Calibration

Heterogeneous SoC devices, including sensors, analogue and mixed-signal front-end circuits and the availability of massive digital processing capability, are being increasingly used in safety-critical applications like in the automotive, medical, and the security arena. Already a significant amount of attention has been paid in literature with respect to the dependability of the digital parts in heterogeneous SoCs. This is in contrast to especially the sensors and front-end mixed-signal electronics; these are however particular sensitive to external influences over time and hence determining their dependability. This paper provides an integrated SoC/IP approach to enhance the dependability. It will give an example of a digitally-assisted mixed-signal front-end IP which is being evaluated under its mission profile of an automotive tyre pressure monitoring system. It will be shown how internal monitoring and digitally-controlled adaptation by using embedded processors can help in terms of improving the dependability of this mixed-signal part under harsh conditions for a long time

Space Station Furnace Facility. Volume 2: Requirements definition and conceptual design study

The Space Station Freedom Furnace (SSFF) Project is divided into two phases: phase 1, a definition study phase, and phase 2, a design and development phase. TBE was awarded a research study entitled, 'Space Station Furnace Facility Requirements Definition and Conceptual Design Study' on June 2, 1989. This report addresses the definition study phase only. Phase 2 is to be complete after completion of phase 1. The contract encompassed a requirements definition study and culminated in hardware/facility conceptual designs and hardware demonstration development models to test these conceptual designs. The study was divided into two parts. Part 1 (the basic part of the effort) encompassed preliminary requirements definition and assessment; conceptional design of the SSFF Core; fabrication of mockups; and preparation for the support of a conceptional design review (CoDR). Part 2 (the optional part of the effort) included detailed definition of the engineering and design requirements, as derived from the science requirements; refinement of the conceptual design of the SSFF Core; fabrication and testing of the 'breadboards' or development models; and preparation for and support of a requirements definition review

Design and implementation of an integrated surface texture information system for design, manufacture and measurement

The optimised design and reliable measurement of surface texture are essential to guarantee the functional performance of a geometric product. Current support tools are however often limited in functionality, integrity and efficiency. In this paper, an integrated surface texture information system for design, manufacture and measurement, called “CatSurf”, has been designed and developed, which aims to facilitate rapid and flexible manufacturing requirements. A category theory based knowledge acquisition and knowledge representation mechanism has been devised to retrieve and organize knowledge from various Geometrical Product Specifications (GPS) documents in surface texture. Two modules (for profile and areal surface texture) each with five components are developed in the CatSurf. It also focuses on integrating the surface texture information into a Computer-aided Technology (CAx) framework. Two test cases demonstrate design process of specifications for the profile and areal surface texture in AutoCAD and SolidWorks environments respectively

A system-on-chip digital pH meter for use in a wireless diagnostic capsule

This paper describes the design and implementation of a system-on-chip digital pH meter, for use in a wireless capsule application. The system is organized around an 8-bit microcontroller, designed to be functionally identical to the Motorola 6805. The analog subsystem contains a floating-electrode ISFET, which is fully compatible with a commercial CMOS process. On-chip programmable voltage references and multiplexors permit flexibility with the minimum of external connections. The chip is designed in a modular fashion to facilitate verification and component re-use. The single-chip pH meter can be directly connected to a personal computer, and gives a response of 37 bits/pH, within an operating range of 7 pH units

Avionics test bed development plan

A development plan for a proposed avionics test bed facility for the early investigation and evaluation of new concepts for the control of large space structures, orbiter attached flex body experiments, and orbiter enhancements is presented. A distributed data processing facility that utilizes the current laboratory resources for the test bed development is outlined. Future studies required for implementation, the management system for project control, and the baseline system configuration are defined. A background analysis of the specific hardware system for the preliminary baseline avionics test bed system is included

Innovative teaching of IC design and manufacture using the Superchip platform

In this paper we describe how an intelligent chip architecture has allowed a large cohort of undergraduate students to be given effective practical insight into IC design by designing and manufacturing their own ICs. To achieve this, an efficient chip architecture, the “Superchip”, has been developed, which allows multiple student designs to be fabricated on a single IC, and encapsulated in a standard package without excessive cost in terms of time or resources. We demonstrate how the practical process has been tightly coupled with theoretical aspects of the degree course and how transferable skills are incorporated into the design exercise. Furthermore, the students are introduced at an early stage to the key concepts of team working, exposure to real deadlines and collaborative report writing. This paper provides details of the teaching rationale, design exercise overview, design process, chip architecture and test regime