Analogue-to-digital conversion and image enhancement using neuron-mos technology

This thesis describes the development of two novel circuits that use a newly developed technology, that of neuron-MOS, for the purposes of analogue-to-digital conversion and image enhancement. Neuron-MOS has the potential to reduce both the complexity and number of transistors required for analogue and digital circuits. A reduced area, low transistor-count- analogue-to-digital converter that is suitable for inclusion in a massively parallel array of identical image processing elements is developed. Supporting the function of the array some fundamental image enhancement operations, such as edge enhancement, are examined exploiting the unique features of neuron-MOS technology

A νMOS soft-maximum current mirror

In this paper, we describe a novel circuit consisting of N+1 MOS transistors and a single floating gate which computes a soft maximum of N current inputs and reflects the result in the output transistor. An intuitive description of the operation of the circuit is given. Data from a working two-input version of the circuit is presented and discussed. The circuit features a high output voltage swing and an interesting feedback mechanism which causes its output impedance to be comparable to that of a normal MOS transistor despite the fact that the output device is a floating-gate transistor

NASA Tech Briefs Index, 1977, volume 2, numbers 1-4

Announcements of new technology derived from the research and development activities of NASA are presented. Abstracts, and indexes for subject, personal author, originating center, and Tech Brief number are presented for 1977

Stabilising Semiconducting Polymers Using Solid State Molecular Additives

Solution processed organic semiconductors contain extrinsic environmental species that cause device instabilities as they are difficult to remove during low temperature processing and are able to penetrate into organic electronics after fabrication. This dissertation is centered on the search for and development of solid state molecular additives to improve device stability associated with atmospheric defects in organic field effect transistors. To achieve this, an extended study was undertaken of the influence of over 95 different molecular additives expected to improve the stability characteristics of organic field effect transistors based on the literature. This dissertation demonstrates that positive bias and light stress stability can be improved in both p-type diF-TES ADT and IDT-BT organic field effect transistors by incorporating solid state small molecular additives. Simulations predict that the additives improve stability by introducing a competitive recombination pathway in order to prevent the trapping of electrons in the LUMO of the semiconductor by atmospheric species. Improvements with the solid state molecular additives are achieved by controlling the LUMO and morphology of the additive polymer blend. Secondly, improvements in the environmental and negative bias stress stability of organic field effect transistors are also observed with molecular additives. The solid state small molecular additives that significantly improve device characteristics are limited to a subset of molecules with similar structure to tetracyanoquinodimethane. It is demonstrated that this subset of solid state molecular additives correlates with a chemical reaction between the molecules and water. The chemical reaction appears to change the molecular additives into a new chemical species, plausibly consuming water, modifying the pH and doping the semiconductor, resulting in improved organic field effect transistor characteristics. Thirdly, machine learning techniques are used to accurately predict which solid state additives are capable of improving device performance. The machine learning algorithm uses neural passing networks for feature generation, due to its ability to capture physical plausible features such as functional groups. The algorithm screened over 1.5 billion molecular structures and found plausible molecular structures based on expert knowledge. Fourthly, novel analogue neuromorphic computer architectures based on anti-ferromagnetic and analogue transistors are modeled. The proposed architecture presents both trainable anti-ferromagnetic based synapses for learning and non-trainable voltage controlled synapses for computationally demanding inferences. This dissertation suggests that combining both the fully controllable and trainable networks is a promising route forward for analog neuromorphic computers.FlexEnable Christ's College Canadian Centennial Scholarship Fun

Overview study of Space Power Technologies for the advanced energetics program

Space power technologies are reviewed to determine the state-of-the-art and to identify advanced or novel concepts which promise large increases in performance. The potential for incresed performance is judged relative to benchmarks based on technologies which have been flight tested. Space power technology concepts selected for their potentially high performance are prioritized in a list of R & D topical recommendations for the NASA program on Advanced Energetics. The technology categories studied are solar collection, nuclear power sources, energy conversion, energy storage, power transmission, and power processing. The emphasis is on electric power generation in space for satellite on board electric power, for electric propulsion, or for beamed power to spacecraft. Generic mission categories such as low Earth orbit missions and geosynchronous orbit missions are used to distinguish general requirements placed on the performance of power conversion technology. Each space power technology is judged on its own merits without reference to specific missions or power systems. Recommendations include 31 space power concepts which span the entire collection of technology categories studied and represent the critical technologies needed for higher power, lighter weight, more efficient power conversion in space

Instruments on large optical telescopes -- A case study

In the distant past, telescopes were known, first and foremost, for the sizes of their apertures. Advances in technology are now enabling astronomers to build extremely powerful instruments to the extent that instruments have now achieved importance comparable or even exceeding the usual importance accorded to the apertures of the telescopes. However, the cost of successive generations of instruments has risen at a rate noticeably above that of the rate of inflation. Here, given the vast sums of money now being expended on optical telescopes and their instrumentation, I argue that astronomers must undertake "cost-benefit" analysis for future planning. I use the scientific output of the first two decades of the W. M. Keck Observatory as a laboratory for this purpose. I find, in the absence of upgrades, that the time to reach peak paper production for an instrument is about six years. The prime lifetime of instruments (sans upgrades), as measured by citations returns, is about a decade. Well thought out and timely upgrades increase and sometimes even double the useful lifetime. I investigate how well instrument builders are rewarded. I find acknowledgements ranging from almost 100% to as low as 60%. Next, given the increasing cost of operating optical telescopes, the management of existing observatories continue to seek new partnerships. This naturally raises the question "What is the cost of a single night of telescope time". I provide a rational basis to compute this quantity. I then end the paper with some thoughts on the future of large ground-based optical telescopes, bearing in mind the explosion of synoptic precision photometric, astrometric and imaging surveys across the electromagnetic spectrum, the increasing cost of instrumentation and the rise of mega instruments.Comment: Revised from previous submission (typos fixed, table 6 was garbled). Submitted to PAS

Power supply current [IPS] based testing of CMOS amplifier circuit with and without floating gate input transistors

This work presents a case study, which attempts to improve the fault diagnosis and testability of the power supply current based testing methodology applied to a typical two-stage CMOS operational amplifier and is extended to operational amplifier with floating gate input transistors*. The proposed test method takes the advantage of good fault coverage through the use of a simple power supply current measurement based test technique, which only needs an ac input stimulus at the input and no additional circuitry. The faults simulating possible manufacturing defects have been introduced using the fault injection transistors. In the present work, variations of ac ripple in the power supply current IPS, passing through VDD under the application of an ac input stimulus is measured to detect injected faults in the CMOS amplifier. The effect of parametric variation is taken into consideration by setting tolerance limit of ± 5% on the fault-free IPS value. The fault is identified if the power supply current, IPS falls outside the deviation given by the tolerance limit. This method presented can also be generalized to the test structures of other floating-gate MOS analog and mixed signal integrated circuits

NASA Tech Briefs, Winter 1977

Topics include: NASA TU Services: Technology Utilization services that can assist you in learning about and applying NASA technology; New Product Ideas: A summary of selected innovations of value to manufacturers for the development of new products; Electronic Components and Circuits; Electronic Systems; Physical Sciences; Materials; Life Sciences; Mechanics; Machinery; Fabrication Technology; Mathematics and Information Sciences

First order sigma-delta modulator of an oversampling ADC design in CMOS using floating gate MOSFETS

We report a new architecture for a sigma-delta oversampling analog-to-digital converter (ADC) in which the first order modulator is realized using the floating gate MOSFETs at the input stage of an integrator and the comparator. The first order modulator is designed using an 8 MHz sampling clock frequency and implemented in a standard 1.5µm n-well CMOS process. The decimator is an off-chip sinc-filter and is programmed using the VERILOG and tested with Altera Flex EPF10K70RC240 FPGA board. The ADC gives an 8-bit resolution with a 65 kHz bandwidth

A microprocessor based telemetry outstation

This thesis describes the development of a microprocessor based telemetry outstation used to collect analogue and digital data at remote sites for the Cape Town City Council's Waterworks Branch of the City Engineer's Department. It is a functional equivalent of existing vendor supplied outstations which are not microprocessor based i.e. they rely purely on hardware. It was necessary to develop these units in-house due mainly to cost considerations since the vendor supplied units were becoming increasingly expensive; furthermore, they are using obsolescent technology and the purchase of spare parts has become increasingly difficult. This latter situation has been aggravated in more recent times by the threat of sanctions. The expertise gained by the writer from the development phase has already been directly applicable to another telemetry project for the Cape Town City Council. This dramatically shortened the development time. Further projects of this nature are envisaged. The outstation collects dam level and water flow rate values and alarms at remote sites, most of them reservoirs. In addition, the flow rates are integrated with respect to time to give volumes. These quantities are transmitted back to the master station via a modem and u.h.f. tranceiver when interrogated by a master station. The development of the outstation involved a detailed analysis of the telemetry protocol between the master station and five existing outstations. A complete set of general purpose hardware modules had to be designed with future applications in mind, a software philosophy formulated, implemented and tested and extensive field testing and evaluation performed before production of sixteen units commenced. All the development work was done in the Computer Section of the City Electrical Engineer's Department in Cape Town