Improved Reliability of FPGA-based PUF Identification Generator Design

Physical unclonable functions (PUFs), a form of physical security primitive, enable digital identifiers to be extracted from devices, such as field programmable gate arrays (FPGAs). Many PUF implementations have been proposed to generate these unique n -bit binary strings. However, they often offer insufficient uniqueness and reliability when implemented on FPGAs and can consume excessive resources. To address these problems, in this article we present an efficient, lightweight, and scalable PUF identification (ID) generator circuit that offers a compact design with good uniqueness and reliability properties and is specifically designed for FPGAs. A novel post-characterisation methodology is also proposed that improves the reliability of a PUF without the need for any additional hardware resources. Moreover, the proposed post-characterisation method can be generally used for any FPGA-based PUF designs. The PUF ID generator consumes 8.95% of the hardware resources of a low-cost Xilinx Spartan-6 LX9 FPGA and 0.81% of a Xilinx Artix-7 FPGA. Experimental results show good uniqueness, reliability, and uniformity with no occurrence of bit-aliasing. In particular, the reliability of the PUF is close to 100% over an environmental temperature range of 25°C to 70°C with ± 10% variation in the supply voltage. </jats:p

Trigger design studies at future high-luminosity colliders

The LHC will enter in 2026 its high-luminosity phase which will deliver a peak instantaneous luminosity of $7.5 \times 10^{34}$ cm$^{-2}$ s$^{-1}$ and produce events with an average pile-up of 200. In order to pursue its ambitious physics programme, the CMS experiment will undergo a major upgrade. The level-1 trigger will be replaced with a new system able to run the particle flow algorithm. An algorithm that reconstructs jets and computes energy sums from particles found by the particle flow algorithm is presented in this thesis. The algorithm is able to provide similar performance to offline reconstruction and keep the same $p_{\mathrm{T}}$ threshold as in the previous CMS runs. The algorithm was implemented in firmware and tested on Xilinx FPGA. An agreement rate of 96% was obtained in a small-scale demonstrator setup running on a Xilinx FPGA. The full-scale algorithm is expected to use around 41.5% of LUTs, 11.6% of flip-flops, and 2.9% of DSPs of a Xilinx VU9P FPGA running at the frequency of 360 MHz. The FCC-hh project studies the feasibility of a hadron collider operating at the centre-of-mass energy of 100 TeV after the LHC operations have ended. The collider is expected to operate at a base instantaneous luminosity of $5 \times 10^{34}$ cm$^{-2}$ s$^{-1}$, and reach a peak value of $30 \times 10^{34}$ cm$^{-2}$ s$^{-1}$ corresponding to an average pile-up of 200 and 1000, respectively. Rates of a trigger system of a detector at FCC-hh were estimated by scaling rates of the Phase-2 CMS level-1 trigger and by developing a parameterised simulation of the Phase-1 trigger system. The results showed that at the instantaneous luminosity of $5 \times 10^{34}$ cm$^{-2}$ s$^{-1}$ the 100-kHz $p_{\mathrm{T}}$ threshold is expected at 85 GeV, 170 GeV, and 350 GeV for single muon, e/$\gamma$, and jet triggers, respectively

A Binaural Neuromorphic Auditory Sensor for FPGA: A Spike Signal Processing Approach

This paper presents a new architecture, design flow, and field-programmable gate array (FPGA) implementation analysis of a neuromorphic binaural auditory sensor, designed completely in the spike domain. Unlike digital cochleae that decompose audio signals using classical digital signal processing techniques, the model presented in this paper processes information directly encoded as spikes using pulse frequency modulation and provides a set of frequency-decomposed audio information using an address-event representation interface. In this case, a systematic approach to design led to a generic process for building, tuning, and implementing audio frequency decomposers with different features, facilitating synthesis with custom features. This allows researchers to implement their own parameterized neuromorphic auditory systems in a low-cost FPGA in order to study the audio processing and learning activity that takes place in the brain. In this paper, we present a 64-channel binaural neuromorphic auditory system implemented in a Virtex-5 FPGA using a commercial development board. The system was excited with a diverse set of audio signals in order to analyze its response and characterize its features. The neuromorphic auditory system response times and frequencies are reported. The experimental results of the proposed system implementation with 64-channel stereo are: a frequency range between 9.6 Hz and 14.6 kHz (adjustable), a maximum output event rate of 2.19 Mevents/s, a power consumption of 29.7 mW, the slices requirements of 11 141, and a system clock frequency of 27 MHz.Ministerio de Economía y Competitividad TEC2012-37868-C04-02Junta de Andalucía P12-TIC-130

An Embedded Biometric Sensor for Ubiquitous Authentication

Communication networks and distributed technologies move people towards the era of ubiquitous computing. An ubiquitous environment needs many authentication sensors for users recognition, in order to provide a secure infrastructure for both user access to resources and services and information management. Today the security requirements must ensure secure and trusted user information to protect sensitive data resource access and they could be used for user traceability inside the platform. Conventional authentication systems, based on username and password, are in crisis since they are not able to guarantee a suitable security level for several applications. Biometric authentication systems represent a valid alternative to the conventional authentication systems providing a flexible einfrastructure towards an integrated solution supporting the requirement for improved inter-organizational functionality. In this work the study and the implementation of a fingerprintsbased embedded biometric system is proposed. Typical strategies implemented in Identity Management Systems could be useful to protect biometric information. The proposed sensor can be seen as a self-contained sensor: it performs the all elaboration steps on board, a necessary requisite to strengthen security, so that sensible data are securely managed and stored inside the sensor, without any data leaking out. The sensor has been prototyped via an FPGA-based platform achieving fast execution time and a good final throughput. Resources used, elaboration times of the sensor are reported. Finally, recognition rates of the proposed embedded biometric sensor have been evaluated considering three different databases: the FVC2002 reference database, the CSAI/Biometrika proprietary database, and the CSAI/Secugen proprietary database. The best achieved FAR and FRR indexes are respectively 1.07% and 8.33%, with an elaboration time of 183.32 ms and a working frequency of 22.5 MHz

Hardware Accelerated DNA Sequencing

DNA sequencing technology is quickly evolving. The latest developments ex- ploit nanopore sensing and microelectronics to realize real-time, hand-held devices. A critical limitation in these portable sequencing machines is the requirement of powerful data processing consoles, a need incompatible with portability and wide deployment. This thesis proposes a rst step towards addressing this problem, the construction of specialized computing modules { hardware accelerators { that can execute the required computations in real-time, within a small footprint, and at a fraction of the power needed by conventional computers. Such a hardware accel- erator, in FPGA form, is introduced and optimized specically for the basecalling function of the DNA sequencing pipeline. Key basecalling computations are identi- ed and ported to custom FPGA hardware. Remaining basecalling operations are maintained in a traditional CPU which maintains constant communications with its FPGA accelerator over the PCIe bus. Measured results demonstrated a 137X basecalling speed improvement over CPU-only methods while consuming 17X less power than a CPU-only method

Design and Evaluation of FPGA-based Hybrid Physically Unclonable Functions

A Physically Unclonable Function (PUF) is a new and promising approach to provide security for physical systems and to address the problems associated with traditional approaches. One of the most important performance metrics of a PUF is the randomness of its generated response, which is presented via uniqueness, uniformity, and bit-aliasing. In this study, we implement three known PUF schemes on an FPGA platform, namely SR Latch PUF, Basic RO PUF, and Anderson PUF. We then perform a thorough statistical analysis on their performance. In addition, we propose the idea of the Hybrid PUF structure in which two (or more) sources of randomness are combined in a way to improve randomness. We investigate two methods in combining the sources of randomness and we show that the second one improves the randomness of the response, significantly. For example, in the case of combining the Basic RO PUF and the Anderson PUF, the Hybrid PUF uniqueness is increased nearly 8%, without any pre-processing or post-processing tasks required. Two main categories of applications for PUFs have been introduced and analyzed: authentication and secret key generation. In this study, we introduce another important application for PUFs. In fact, we develop a secret sharing scheme using a PUF to increase the information rate and provide cheater detection capability for the system. We show that, using the proposed method, the information rate of the secret sharing scheme will improve significantly

Architecture and performance of the KM3NeT front-end firmware

The authors acknowledge the financial support of the funding agencies: Agence Nationale de la Recherche (contract ANR-15-CE31-0020), Centre National de la Recherche Scientifique (CNRS), Commission Europeenne (FEDER fund and Marie Curie Program), Institut Universitaire de France (IUF), LabEx UnivEarthS (ANR-10-LABX-0023 and ANR-18-IDEX-0001), Paris Ile-de-France Region, France; Shota Rustaveli National Science Foundation of Georgia (SRNSFG, FR-18-1268), Georgia; Deutsche Forschungsgemeinschaft (DFG), Germany; The General Secretariat of Research and Technology (GSRT), Greece; Istituto Nazionale di Fisica Nucleare (INFN), Ministero dell'Istruzione, dell'Universita e della Ricerca (MIUR), PRIN 2017 program (Grant NAT-NET 2017W4HA7S) Italy; Ministry of Higher Education Scientific Research and Professional Training, ICTP through Grant AF-13, Morocco; Nederlandse organisatie voor Wetenschappelijk Onderzoek (NWO), the Netherlands; The National Science Centre, Poland (2015/18/E/ST2/00758); National Authority for Scientific Research (ANCS), Romania; Ministerio de Ciencia, Innovacion, Investigacion y Universidades (MCIU): Programa Estatal de Generacion de Conocimiento (refs. PGC2018-096663-B-C41, -A-C42, -B-C43, -B-C44) (MCIU/FEDER), Severo Ochoa Centre of Excellence and MultiDark Consolider (MCIU), Junta de Andalucia (ref. SOMM17/6104/UGR), Generalitat Valenciana: Grisolia (ref. GRISOLIA/2018/119) and GenT (ref. CIDEGENT/2018/034) programs, La Caixa Foundation (ref. LCF/BQ/IN17/11620019), EU: MSC program (ref. 713673), Spain.The KM3NeT infrastructure consists of two deep-sea neutrino telescopes being deployed in the Mediterranean Sea. The telescopes will detect extraterrestrial and atmospheric neutrinos by means of the incident photons induced by the passage of relativistic charged particles through the seawater as a consequence of a neutrino interaction. The telescopes are configured in a three-dimensional grid of digital optical modules, each hosting 31 photomultipliers. The photomultiplier signals produced by the incident Cherenkov photons are converted into digital information consisting of the integrated pulse duration and the time at which it surpasses a chosen threshold. The digitization is done by means of time to digital converters (TDCs) embedded in the field programmable gate array of the central logic board. Subsequently, a state machine formats the acquired data for its transmission to shore. We present the architecture and performance of the front-end firmware consisting of the TDCs and the state machine.French National Research Agency (ANR) ANR-15-CE31-0020Centre National de la Recherche Scientifique (CNRS)Commission Europeenne (FEDER fund), FranceCommission Europeenne (Marie Curie Program), FranceInstitut Universitaire de France (IUF), FranceLabEx UnivEarthS, France ANR-10-LABX-0023 ANR-18-IDEX-0001Paris Ile-de-France Region, FranceShota Rustaveli National Science Foundation of Georgia (SRNSFG), Georgia FR-18-1268German Research Foundation (DFG)Greek Ministry of Development-GSRTIstituto Nazionale di Fisica Nucleare (INFN) NAT-NET 2017W4HA7SMinistry of Education, Universities and Research (MIUR) NAT-NET 2017W4HA7SPRIN 2017 program Italy NAT-NET 2017W4HA7SMinistry of Higher Education Scientific Research and Professional Training, ICTP, Morocco AF-13Netherlands Organization for Scientific Research (NWO) Netherlands GovernmentNational Science Centre, Poland 2015/18/E/ST2/00758National Authority for Scientific Research (ANCS), RomaniaMinisterio de Ciencia, Innovacion, Investigacion y Universidades (MCIU): Programa Estatal de Generacion de Conocimiento (MCIU/FEDER), Spain PGC2018-096663-B-C41 PGC2018-096663-A-C42 PGC2018-096663-B-C43 PGC2018-096663-B-C44Severo Ochoa Centre of Excellence and MultiDark Consolider (MCIU), SpainJunta de Andalucia European Commission SOMM17/6104/UGRGeneralitat Valenciana: Grisolia program, Spain GRISOLIA/2018/119Generalitat Valenciana: GenT program, Spain CIDEGENT/2018/034La Caixa Foundation LCF/BQ/IN17/11620019EU: MSC program, Spain 71367

AHEAD: Automatic Holistic Energy-Aware Design Methodology for MLP Neural Network Hardware Generation in Proactive BMI Edge Devices

The prediction of a high-level cognitive function based on a proactive brain–machine interface (BMI) control edge device is an emerging technology for improving the quality of life for disabled people. However, maintaining the stability of multiunit neural recordings is made difficult by the nonstationary nature of neurons and can affect the overall performance of proactive BMI control. Thus, it requires regular recalibration to retrain a neural network decoder for proactive control. However, retraining may lead to changes in the network parameters, such as the network topology. In terms of the hardware implementation of the neural decoder for real-time and low-power processing, it takes time to modify or redesign the hardware accelerator. Consequently, handling the engineering change of the low-power hardware design requires substantial human resources and time. To address this design challenge, this work proposes AHEAD: an automatic holistic energy-aware design methodology for multilayer perceptron (MLP) neural network hardware generation in proactive BMI edge devices. By taking a holistic analysis of the proactive BMI design flow, the approach makes judicious use of the intelligent bit-width identification (BWID) and configurable hardware generation, which autonomously integrate to generate the low-power hardware decoder. The proposed AHEAD methodology begins with the trained MLP parameters and golden datasets and produces an efficient hardware design in terms of performance, power, and area (PPA) with the least loss of accuracy. The results show that the proposed methodology is up to a 4X faster in performance, 3X lower in terms of power consumption, and achieves a 5X reduction in area resources, with exact accuracy, compared to floating-point and half-floating-point design on a field-programmable gate array (FPGA), which makes it a promising design methodology for proactive BMI edge devices