Fbb Cmos Tapered Buffer With Optimal Vth Selection

This paper represents fixed body biased CMOS Tapered Buffer which is designed to minimize the PDP (Power Delay Product) of the circuit. CMOS Tapered Buffers are often used for driving large capacitive load at high speed. Since there are tradeoffs between performance parameters of Buffer for minimizing its PDP value and due to technology constraints on the threshold voltage of MOS; one can vary the Vth up to certain limit while keeping the VDD constant. The proposed work is helpful in designing power efficient CMOS Tapered Buffer. This is found that in proposed Buffer when Vth value for the first stage of inverter is taken between the range of (0.2VDD - 0.4 VDD), its performance gets improved in terms of power dissipation. This analysis is verified by simulating the 2-stage Tapered buffer using standard 180nm CMOS technology in Cadence environment. Analysis performed on the schematic shows that FBB (Fixed Body Bias) Tapered Buffer reduces the average power dissipation across capacitive load by 77% and static power has been reduced to 18.3% at very less penalty in delay. Hence the proposed approach is suitable in the design of low power buffer for increasing the current capability of logic gate at optimal speed

Optimization Opportunities in RRAM-based FPGA Architectures

Static Random Access Memory (SRAM)-based routing multiplexers, whatever structure is employed, share a common limitation: their area, delay and power increase linearly with the input size. This property results in most SRAM-based FPGA architectures typically avoiding the use of large multiplexers. Resistive Random Access Memory (RRAM)- based multiplexers, built with one-level structure, have a unique advantage over SRAM-based multiplexers: their ideal delay is independent from the input size. This property allows RRAM-based FPGA architectures to use larger multiplexers than their SRAM-based counterparts, without generating any delay overhead. In this paper, by carefully considering the properties of RRAM multiplexers, we assess that current state-of-art architectural parameters for SRAM-based FPGAs cannot preserve optimality in the context of RRAM-based FPGAs. As a result, we propose that in RRAM-based FPGAs, (a) the routing tracks should be interconnected to Look-Up Table (LUT) inputs via a one-level crossbar, instead of through Connection Blocks and local routing; (b) the Switch Blocks should employ larger multiplexers; (c) length-2 wires should be used instead of length-4 wires. When operated in nominal voltage, the proposed RRAM-based FPGA architecture reduces area by 26%, delay by 39% and channel width by 13%, as compared to a SRAM-based FPGA with a classical architecture. When operated in the near-Vt regime, the proposed RRAM-based FPGA architecture improves Area-Delay Product by 42% and Power-Delay Product by 5x as compared to a classical SRAM-based FPGA at nominal voltage

Switched-capacitor step-down rectifier for low-voltage power conversion

This paper presents a switched-capacitor rectifier that provides step down voltage conversion from an ac input voltage to a dc output. Coupled with current-drive source, low-loss and high step-down rectification is realized. Implementation in CMOS with appropriate controls results in a design suitable for low-voltage very-high-frequency conversion. Applications include switched-capacitor rectification to convert high-frequency ac to a dc output and, combined with inversion and transformation, to dc-dc converters for low-voltage outputs. A two-step CMOS integrated full-bridge switched-capacitor rectifier is implemented in TSMC 0.25 μm CMOS technology for demonstration purposes. For an operation frequency of 50 MHz and an output voltage of 2.5 V, the peak efficiency of the rectifier is 81% at a power level of 4 W.Interconnect Focus Center (United States. Defense Advanced Research Projects Agency and Semiconductor Research Corporation

Circuit Design, Architecture and CAD for RRAM-based FPGAs

Field Programmable Gate Arrays (FPGAs) have been indispensable components of embedded systems and datacenter infrastructures. However, energy efficiency of FPGAs has become a hard barrier preventing their expansion to more application contexts, due to two physical limitations: (1) The massive usage of routing multiplexers causes delay and power overheads as compared to ASICs. To reduce their power consumption, FPGAs have to operate at low supply voltage but sacrifice performance because the transistors drive degrade when working voltage decreases. (2) Using volatile memory technology forces FPGAs to lose configurations when powered off and to be reconfigured at each power on. Resistive Random Access Memories (RRAMs) have strong potentials in overcoming the physical limitations of conventional FPGAs. First of all, RRAMs grant FPGAs non-volatility, enabling FPGAs to be "Normally powered off, Instantly powered on". Second, by combining functionality of memory and pass-gate logic in one unique device, RRAMs can greatly reduce area and delay of routing elements. Third, when RRAMs are embedded into datpaths, the performance of circuits can be independent from their working voltage, beyond the limitations of CMOS circuits. However, researches and development of RRAM-based FPGAs are in their infancy. Most of area and performance predictions were achieved without solid circuit-level simulations and sophisticated Computer Aided Design (CAD) tools, causing the predicted improvements to be less convincing. In this thesis,we present high-performance and low-power RRAM-based FPGAs fromtransistorlevel circuit designs to architecture-level optimizations and CAD tools, using theoretical analysis, industrial electrical simulators and novel CAD tools. We believe that this is the first systematic study in the field, covering: From a circuit design perspective, we propose efficient RRAM-based programming circuits and routing multiplexers through both theoretical analysis and electrical simulations. The proposed 4T(ransitor)1R(RAM) programming structure demonstrates significant improvements in programming current, when compared to most popular 2T1R programming structure. 4T1R-based routingmultiplexer designs are proposed by considering various physical design parasitics, such as intrinsic capacitance of RRAMs and wells doping organization. The proposed 4T1R-based multiplexers outperformbest CMOS implementations significantly in area, delay and power at both nominal and near-Vt regime. From a CAD perspective, we develop a generic FPGA architecture exploration tool, FPGASPICE, modeling a full FPGA fabric with SPICE and Verilog netlists. FPGA-SPICE provides different levels of testbenches and techniques to split large SPICE netlists, in order to obtain better trade-off between simulation time and accuracy. FPGA-SPICE can capture area and power characteristics of SRAM-based and RRAM-based FPGAs more accurately than the currently best analyticalmodels. From an architecture perspective, we propose architecture-level optimizations for RRAMbased FPGAs and quantify their minimumrequirements for RRAM devices. Compared to the best SRAM-based FPGAs, an optimized RRAM-based FPGA architecture brings significant reduction in area, delay and power respectively. In particular, RRAM-based FPGAs operating in the near-Vt regime demonstrate a 5x power improvement without delay overhead as compared to optimized SRAM-based FPGA operating at nominal working voltage

High efficiency wide-band line drivers in low voltage CMOS using Class-D techniques

In this thesis, the applicability of Class-D amplifiers to integrated wide-band communication line driver applications is studied. While Class-D techniques can address some of the efficiency limitations of linear amplifier structures and have shown promising results in low frequency applications, the low frequency techniques and knowledge need further development in order to improve their practicality for wide band systems. New structures and techniques to extend the application of Class-D to wide-band communication systems, in particular the HomePlug AV wire- line communication standard, will be proposed. Additionally, the digital processing requirements of these wide-band systems drives rapid movement towards nanometer technology nodes and presents new challenges which will be addressed, and new opportunities which will be exploited, for wide-band integrated Class-D line drivers. There are three main contributions of this research. First, a model of Class-D efficiency degradation mechanisms is created, which allows the impact of high-level design choices such as supply voltage, process technology and operating frequency to be assessed. The outcome of this section is a strategy for pushing the high efficiency of Class-D to wide band communication applications, with switching frequencies up to many hundreds of Megahertz. A second part of this research considers the design of efficient, fast and high power Class-D output stages, as these are the major efficiency and bandwidth bottleneck in wide-band applications. A novel NMOS-only totem pole output stage with a fast, integrated drive structure will be proposed. In a third section, a complete wide-band Class-D line driver is designed in a 0.13μm digital CMOS process. The line driver is systematically designed using a rigorous development methodology and the aims are to maximise the achievable signal bandwidth while minimising power dissipation. Novel circuits and circuit structures are proposed as part of this section and the resulting fabricated Class-D line driver test chip shows an efficiency of 15% while driving a 30MHz wide signal with an MTPR of 22dB, at 33mW injected power

Offline Recognition of Malayalam and Kannada Handwritten Documents Using Deep Learning

For a variety of reasons, handwritten text can be digitalized. It is used in a variety of government entities, including banks, post offices, and archaeological departments. Handwriting recognition, on the other hand, is a difficult task as everyone has a different writing style. There are essentially two methods for handwritten recognition: a holistic and an analytic approach. The previous methods of handwriting recognition are time- consuming. However, as deep neural networks have progressed, the approach has become more straightforward than previous methods. Furthermore, the bulk of existing solutions are limited to a single language. To recognise multilanguage handwritten manuscripts offline, this work employs an analytic approach. It describes how to convert Malayalam and Kannada handwritten manuscripts into editable text. Lines are separated from the input document first. After that, word segmentation is performed. Finally, each word is broken down into individual characters. An artificial neural network is utilised for feature extraction and classification. After that, the result is converted to a word document

Design tradeoffs and challenges in practical coherent optical transceiver implementations

This tutorial discusses the design and ASIC implementation of coherent optical transceivers. Algorithmic and architectural options and tradeoffs between performance and complexity/power dissipation are presented. Particular emphasis is placed on flexible (or reconfigurable) transceivers because of their importance as building blocks of software-defined optical networks. The paper elaborates on some advanced digital signal processing (DSP) techniques such as iterative decoding, which are likely to be applied in future coherent transceivers based on higher order modulations. Complexity and performance of critical DSP blocks such as the forward error correction decoder and the frequency-domain bulk chromatic dispersion equalizer are analyzed in detail. Other important ASIC implementation aspects including physical design, signal and power integrity, and design for testability, are also discussed.Fil: Morero, Damián Alfonso. Universidad Nacional de Córdoba. Facultad de Ciencias Exactas, Físicas y Naturales; Argentina. ClariPhy Argentina S.A.; ArgentinaFil: Castrillon, Alejandro. Universidad Nacional de Córdoba. Facultad de Ciencias Exactas, Físicas y Naturales; ArgentinaFil: Aguirre, Alejandro. ClariPhy Argentina S.A.; ArgentinaFil: Hueda, Mario Rafael. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - Córdoba. Instituto de Estudios Avanzados en Ingeniería y Tecnología. Universidad Nacional de Córdoba. Facultad de Ciencias Exactas Físicas y Naturales. Instituto de Estudios Avanzados en Ingeniería y Tecnología; ArgentinaFil: Agazzi, Oscar Ernesto. Universidad Nacional de Córdoba. Facultad de Ciencias Exactas, Físicas y Naturales; Argentina. ClariPhy Argentina S.A.; Argentin

Physical Design Methodologies for Low Power and Reliable 3D ICs

As the semiconductor industry struggles to maintain its momentum down the path following the Moore's Law, three dimensional integrated circuit (3D IC) technology has emerged as a promising solution to achieve higher integration density, better performance, and lower power consumption. However, despite its significant improvement in electrical performance, 3D IC presents several serious physical design challenges. In this dissertation, we investigate physical design methodologies for 3D ICs with primary focus on two areas: low power 3D clock tree design, and reliability degradation modeling and management. Clock trees are essential parts for digital system which dissipate a large amount of power due to high capacitive loads. The majority of existing 3D clock tree designs focus on minimizing the total wire length, which produces sub-optimal results for power optimization. In this dissertation, we formulate a 3D clock tree design flow which directly optimizes for clock power. Besides, we also investigate the design methodology for clock gating a 3D clock tree, which uses shutdown gates to selectively turn off unnecessary clock activities. Different from the common assumption in 2D ICs that shutdown gates are cheap thus can be applied at every clock node, shutdown gates in 3D ICs introduce additional control TSVs, which compete with clock TSVs for placement resources. We explore the design methodologies to produce the optimal allocation and placement for clock and control TSVs so that the clock power is minimized. We show that the proposed synthesis flow saves significant clock power while accounting for available TSV placement area. Vertical integration also brings new reliability challenges including TSV's electromigration (EM) and several other reliability loss mechanisms caused by TSV-induced stress. These reliability loss models involve complex inter-dependencies between electrical and thermal conditions, which have not been investigated in the past. In this dissertation we set up an electrical/thermal/reliability co-simulation framework to capture the transient of reliability loss in 3D ICs. We further derive and validate an analytical reliability objective function that can be integrated into the 3D placement design flow. The reliability aware placement scheme enables co-design and co-optimization of both the electrical and reliability property, thus improves both the circuit's performance and its lifetime. Our electrical/reliability co-design scheme avoids unnecessary design cycles or application of ad-hoc fixes that lead to sub-optimal performance. Vertical integration also enables stacking DRAM on top of CPU, providing high bandwidth and short latency. However, non-uniform voltage fluctuation and local thermal hotspot in CPU layers are coupled into DRAM layers, causing a non-uniform bit-cell leakage (thereby bit flip) distribution. We propose a performance-power-resilience simulation framework to capture DRAM soft error in 3D multi-core CPU systems. In addition, a dynamic resilience management (DRM) scheme is investigated, which adaptively tunes CPU's operating points to adjust DRAM's voltage noise and thermal condition during runtime. The DRM uses dynamic frequency scaling to achieve a resilience borrow-in strategy, which effectively enhances DRAM's resilience without sacrificing performance. The proposed physical design methodologies should act as important building blocks for 3D ICs and push 3D ICs toward mainstream acceptance in the near future

Development of a Universal MOSFET Gate Impedance Model

Scaling of CMOS technology to 100 nm & below and the endless pursuit of higher operating frequencies drive the need to accurately model effects that dominate at those feature sizes and frequencies. Current modeling techniques are frequency limited and require different models for different frequency ranges in order to achieve accuracy goals. In the foundry world, high frequency models are typically empirical in nature and significantly lag their low frequency counterparts in terms of availability. This tends to slow the adoption of new foundry technologies for high performance applications such as extremely high data rate serializer/deserializer transceiver cores. However, design cycle time and time to market while transitioning between technology nodes can be reduced by incorporating a reusable, industry-standard model. This work proposes such a model for device gate impedance that is simulator-friendly, compact, frequencyindependent, and relatively portable across technology nodes. This semi-empirical gate impedance model is based on depletion in the poly-silicon gate electrode. The effect of device length and single-leg width on the input impedance is studied with the aid of extensive measured data obtained from devices built in 110 nm and 180 nm technologies in the 1-20GHz frequency range. The measured data illustrates that the device input impedance has a non-linear frequency dependency. This variation in input impedance is the result of gate poly-silicon depletion, which can be modeled by an external RC network connected at the gate of the device. Excellent agreement between the simulation results and the measured data validates the model in the device active region for 1-20GHz frequency range. The gate impedance model is further modified by incorporating parasitic effects, extending its range to 200MHz-20GHz. This model performs accurately for 180 run, 110 nm and 90 nm technologies at different bias conditions and dimensions. The model and model parameter behavior are consistent across technology nodes thereby enabling re-usability and portability. The accuracy of this new gate impedance model is demonstrated in various applications: to validate the model extraction techniques for different device configurations, to assess the input data run-length variations on CML buffer performance and to estimate the jitter in ring oscillators