Signaling in 3-D integrated circuits, benefits and challenges

Three-dimensional (3-D) or vertical integration is a design and packaging paradigm that can mitigate many of the increasing challenges related to the design of modern integrated systems. 3-D circuits have recently been at the spotlight, since these circuits provide a potent approach to enhance the performance and integrate diverse functions within amulti-plane stack. Clock networks consume a great portion of the power dissipated in a circuit. Therefore, designing a low-power clock network in synchronous circuits is an important task. This requirement is stricter for 3-D circuits due to the increased power densities. Synchronization issues can be more challenging for 3-D circuits since a clock path can spread across several planes with different physical and electrical characteristics. Consequently, designing low power clock networks for 3-D circuits is an important issue. Resonant clock networks are considered efficient low-power alternatives to conventional clock distribution schemes. These networks utilize additional inductive circuits to reduce power while delivering a full swing clock signal to the sink nodes. In this research, a design method to apply resonant clocking to synthesized clock trees is proposed. Manufacturing processes for 3-D circuits include some additional steps as compared to standard CMOS processes which makes 3-D circuits more susceptible to manufacturing defects and lowers the overall yield of the bonded 3-D stack. Testing is another complicated task for 3-D ICs, where pre-bond test is a prerequisite. Pre-bond testability, in turn, presents new challenges to 3-D clock network design primarily due to the incomplete clock distribution networks prior to the bonding of the planes. A design methodology of resonant 3-D clock networks that support wireless pre-bond testing is introduced. To efficiently address this issue, inductive links are exploited to wirelessly transmit the clock signal to the disjoint resonant clock networks. The inductors comprising the LC tanks are used as the receiver circuit for the links, essentially eliminating the need for additional circuits and/or interconnect resources during pre-bond test. Recent FPGAs are quite complex circuits which provide reconfigurablity at the cost of lower performance and higher power consumption as compared to ASIC circuits. Exploiting a large number of programmable switches, routing structures are mainly responsible for performance degradation in FPAGs. Employing 3-D technology can providemore efficient switches which drastically improve the performance and reduce the power consumption of the FPGA. RRAM switches are one of the most promising candidates to improve the FPGA routing architecture thanks to their low on-resistance and non-volatility. Along with the configurable switches, buffers are the other important element of the FPGAs routing structure. Different characteristics of RRAM switches change the properties of signal paths in RRAM-based FPGAs. The on resistance of RRAMswitches is considerably lower than CMOS pass gate switches which results in lower RC delay for RRAM-based routing paths. This different nature in critical path and signal delay in turn affect the need for intermediate buffers. Thus the buffer allocation should be reconsidered. In the last part of this research, the effect of intermediate buffers on signal propagation delay is studied and a modified buffer allocation scheme for RRAM-based FPGA routing path is proposed

The effects of tree crown plasticity on the structure and dynamics of near-natural beech forests: an individual-based modeling approach

A new individual-based forest model for the species beech (Fagus sylvatica L.) was developed and implemented. The model called BEEch Plasticity (BEEP) describes tree crown plasticity phenomenologically and is able to model aboveground competition for PAR on a process basis. The current debate about the tree interactions in near-natural beech forests and their role in emergent forest structures and dynamics led to the research questions if (1) observed patterns can be modeled and reproduced by only describing the aboveground tree interactions, (2) what effects tree crown plasticity has on the structure and dynamics of near-natural beech forests, and (3) what effects selective thinning has on the structure and dynamics of near-natural beech forests. The BEEP model was developed, parameterized, calibrated, and validated according to data from the unmanaged forest `Schattiner Zuschlag' near Lübeck, North-Germany, while additional data from the sites Langula (Thuringia) and Fabrikschleichach (Bavaria) was used for model parameterization and calibration. Three simulation experiments were conducted. In the first experiment, the BEEP model was run 10 times for 2000 time steps with plastic tree crowns and the emergent forest structure was analyzed using structural indices. In the second experiment, the BEEP model was run again 10 times for 2000 time steps but with a modified crown model that only uses rotation-symmetric tree crowns. In the third experiment, the BEEP model was enhanced with a selective thinning procedure that uses target trees with specific diameter and heights as thinning objects. Forest structure was analyzed through the application of structural indices that capture different aspects of forest structure and by means of characterization of forest development phases. Analysis was accomplished only for the time steps 1000-2000 in order to allow transient oscillation in forest dynamics to develop. The results showed that the focus on aboveground competition and tree interactions sufficed to model beech forests and reproduced a wide range of patterns observed in near-natural and old-growth beech forest. In particular, the BEEP model was able to simulate a multi-layered forest structure with a mosaic structure of several developmental stages on a relatively small area of 0.5 ha. The simulated forest had wide diameter and age distributions. The diameter distribution was reversed-J-shaped. The age range of canopy trees exceeded 200 years. The comparison between simulations with plastic and rotation-symmetric tree crowns revealed that crown plasticity reduced tree competition for crown space and PAR and enhanced the forest structure and heterogeneity in the long term by allowing more tree cohorts of dfferent developmental stages to coexist. This supports the notion that crown plasticity drives beech forest dynamics in near-natural forests. The comparison between simulations with plastic tree crowns and with additional selective thinning showed that thinning does not affect the forest structural heterogeneity and reduces tree crown competition, while spatial patterns of tree positions remained unaltered. However, crown centroids were more regularly distributed. Model assumptions in the submodel routines, especially in the radiation and mortality submodel, question the reliability of the model results, because of the high sensitivity that these routines evoke on model outcomes. Therefore, revised versions of the submodels and a thoroughly validated crown growth model, may produce different results. Thus, the results presented in this study should be treated with care and cannot be used for generalizations about tree interactions in near-natural beech forests

Overcoming the Challenges for Multichip Integration: A Wireless Interconnect Approach

The physical limitations in the area, power density, and yield restrict the scalability of the single-chip multicore system to a relatively small number of cores. Instead of having a large chip, aggregating multiple smaller chips can overcome these physical limitations. Combining multiple dies can be done either by stacking vertically or by placing side-by-side on the same substrate within a single package. However, in order to be widely accepted, both multichip integration techniques need to overcome significant challenges. In the horizontally integrated multichip system, traditional inter-chip I/O does not scale well with technology scaling due to limitations of the pitch. Moreover, to transfer data between cores or memory components from one chip to another, state-of-the-art inter-chip communication over wireline channels require data signals to travel from internal nets to the peripheral I/O ports and then get routed over the inter-chip channels to the I/O port of the destination chip. Following this, the data is finally routed from the I/O to internal nets of the target chip over a wireline interconnect fabric. This multi-hop communication increases energy consumption while decreasing data bandwidth in a multichip system. On the other hand, in vertically integrated multichip system, the high power density resulting from the placement of computational components on top of each other aggravates the thermal issues of the chip leading to degraded performance and reduced reliability. Liquid cooling through microfluidic channels can provide cooling capabilities required for effective management of chip temperatures in vertical integration. However, to reduce the mechanical stresses and at the same time, to ensure temperature uniformity and adequate cooling competencies, the height and width of the microchannels need to be increased. This limits the area available to route Through-Silicon-Vias (TSVs) across the cooling layers and make the co-existence and co-design of TSVs and microchannels extreamly challenging. Research in recent years has demonstrated that on-chip and off-chip wireless interconnects are capable of establishing radio communications within as well as between multiple chips. The primary goal of this dissertation is to propose design principals targeting both horizontally and vertically integrated multichip system to provide high bandwidth, low latency, and energy efficient data communication by utilizing mm-wave wireless interconnects. The proposed solution has two parts: the first part proposes design methodology of a seamless hybrid wired and wireless interconnection network for the horizontally integrated multichip system to enable direct chip-to-chip communication between internal cores. Whereas the second part proposes a Wireless Network-on-Chip (WiNoC) architecture for the vertically integrated multichip system to realize data communication across interlayer microfluidic coolers eliminating the need to place and route signal TSVs through the cooling layers. The integration of wireless interconnect will significantly reduce the complexity of the co-design of TSV based interconnects and microchannel based interlayer cooling. Finally, this dissertation presents a combined trade-off evaluation of such wireless integration system in both horizontal and vertical sense and provides future directions for the design of the multichip system

Climate-Smart Forestry in Mountain Regions

This open access book offers a cross-sectoral reference for both managers and scientists interested in climate-smart forestry, focusing on mountain regions. It provides a comprehensive analysis on forest issues, facilitating the implementation of climate objectives. This book includes structured summaries of each chapter. Funded by the EU’s Horizon 2020 programme, CLIMO has brought together scientists and experts in continental and regional focus assessments through a cross-sectoral approach, facilitating the implementation of climate objectives. CLIMO has provided scientific analysis on issues including criteria and indicators, growth dynamics, management prescriptions, long-term perspectives, monitoring technologies, economic impacts, and governance tools

Roadmap on signal processing for next generation measurement systems

Signal processing is a fundamental component of almost any sensor-enabled system, with a wide range of applications across different scientific disciplines. Time series data, images, and video sequences comprise representative forms of signals that can be enhanced and analysed for information extraction and quantification. The recent advances in artificial intelligence and machine learning are shifting the research attention towards intelligent, data-driven, signal processing. This roadmap presents a critical overview of the state-of-the-art methods and applications aiming to highlight future challenges and research opportunities towards next generation measurement systems. It covers a broad spectrum of topics ranging from basic to industrial research, organized in concise thematic sections that reflect the trends and the impacts of current and future developments per research field. Furthermore, it offers guidance to researchers and funding agencies in identifying new prospects.AerodynamicsMicrowave Sensing, Signals & System

Climate-Smart Forestry in Mountain Regions

This open access book offers a cross-sectoral reference for both managers and scientists interested in climate-smart forestry, focusing on mountain regions. It provides a comprehensive analysis on forest issues, facilitating the implementation of climate objectives. This book includes structured summaries of each chapter. Funded by the EU’s Horizon 2020 programme, CLIMO has brought together scientists and experts in continental and regional focus assessments through a cross-sectoral approach, facilitating the implementation of climate objectives. CLIMO has provided scientific analysis on issues including criteria and indicators, growth dynamics, management prescriptions, long-term perspectives, monitoring technologies, economic impacts, and governance tools

Architectural-Physical Co-Design of 3D CPUs with Micro-Fluidic Cooling

The performance, energy efficiency and cost improvements due to traditional technology scaling have begun to slow down and present diminishing returns. Underlying reasons for this trend include fundamental physical limits of transistor scaling, the growing significance of quantum effects as transistors shrink, and a growing mismatch between transistors and interconnects regarding size, speed and power. Continued Moore's Law scaling will not come from technology scaling alone, and must involve improvements to design tools and development of new disruptive technologies such as 3D integration. 3D integration presents potential improvements to interconnect power and delay by translating the routing problem into a third dimension, and facilitates transistor density scaling independent of technology node. Furthermore, 3D IC technology opens up a new architectural design space of heterogeneously-integrated high-bandwidth CPUs. Vertical integration promises to provide the CPU architectures of the future by integrating high performance processors with on-chip high-bandwidth memory systems and highly connected network-on-chip structures. Such techniques can overcome the well-known CPU performance bottlenecks referred to as memory and communication wall. However the promising improvements to performance and energy efficiency offered by 3D CPUs does not come without cost, both in the financial investments to develop the technology, and the increased complexity of design. Two main limitations to 3D IC technology have been heat removal and TSV reliability. Transistor stacking creates increases in power density, current density and thermal resistance in air cooled packages. Furthermore the technology introduces vertical through silicon vias (TSVs) that create new points of failure in the chip and require development of new BEOL technologies. Although these issues can be controlled to some extent using thermal-reliability aware physical and architectural 3D design techniques, high performance embedded cooling schemes, such as micro-fluidic (MF) cooling, are fundamentally necessary to unlock the true potential of 3D ICs. A new paradigm is being put forth which integrates the computational, electrical, physical, thermal and reliability views of a system. The unification of these diverse aspects of integrated circuits is called Co-Design. Independent design and optimization of each aspect leads to sub-optimal designs due to a lack of understanding of cross-domain interactions and their impacts on the feasibility region of the architectural design space. Co-Design enables optimization across layers with a multi-domain view and thus unlocks new high-performance and energy efficient configurations. Although the co-design paradigm is becoming increasingly necessary in all fields of IC design, it is even more critical in 3D ICs where, as we show, the inter-layer coupling and higher degree of connectivity between components exacerbates the interdependence between architectural parameters, physical design parameters and the multitude of metrics of interest to the designer (i.e. power, performance, temperature and reliability). In this dissertation we present a framework for multi-domain co-simulation and co-optimization of 3D CPU architectures with both air and MF cooling solutions. Finally we propose an approach for design space exploration and modeling within the new Co-Design paradigm, and discuss the possible avenues for improvement of this work in the future

Scanning near-field photon emission microscopy

Ph.DDOCTOR OF PHILOSOPH