NoC Evolution and Performance Optimization by Addition of Long Range Links: A Survey

In the last decade, Networks-on-Chips became the leading edge technology due to the growing requirements of electronic systems. Basically, NoC is an advancement of bus interconnect technology. The challenge is to interconnect existing components such as processors, controllers, and memory arrays in such a way that there is an optimal utilization of communication resources necessitating optimization of the various dominant factors like energy/power consumption, interconnection delay, latency, throughput, etc. In this paper, we focused on the evolution of NoC. Then we studied and have shown through an example that when application specific long-range links are inserted among the tiles whose communication frequencies are high, there is a reduction in the average packet latency and an energy efficient architecture is build up with high throughput. We also discussed the turn model which is deadlock free and the energy model for NoC

Counting to Ten with Two Fingers: Compressed Counting with Spiking Neurons

We consider the task of measuring time with probabilistic threshold gates implemented by bio-inspired spiking neurons. In the model of spiking neural networks, network evolves in discrete rounds, where in each round, neurons fire in pulses in response to a sufficiently high membrane potential. This potential is induced by spikes from neighboring neurons that fired in the previous round, which can have either an excitatory or inhibitory effect. Discovering the underlying mechanisms by which the brain perceives the duration of time is one of the largest open enigma in computational neuro-science. To gain a better algorithmic understanding onto these processes, we introduce the neural timer problem. In this problem, one is given a time parameter t, an input neuron x, and an output neuron y. It is then required to design a minimum sized neural network (measured by the number of auxiliary neurons) in which every spike from x in a given round i, makes the output y fire for the subsequent t consecutive rounds. We first consider a deterministic implementation of a neural timer and show that Theta(log t) (deterministic) threshold gates are both sufficient and necessary. This raised the question of whether randomness can be leveraged to reduce the number of neurons. We answer this question in the affirmative by considering neural timers with spiking neurons where the neuron y is required to fire for t consecutive rounds with probability at least 1-delta, and should stop firing after at most 2t rounds with probability 1-delta for some input parameter delta in (0,1). Our key result is a construction of a neural timer with O(log log 1/delta) spiking neurons. Interestingly, this construction uses only one spiking neuron, while the remaining neurons can be deterministic threshold gates. We complement this construction with a matching lower bound of Omega(min{log log 1/delta, log t}) neurons. This provides the first separation between deterministic and randomized constructions in the setting of spiking neural networks. Finally, we demonstrate the usefulness of compressed counting networks for synchronizing neural networks. In the spirit of distributed synchronizers [Awerbuch-Peleg, FOCS\u2790], we provide a general transformation (or simulation) that can take any synchronized network solution and simulate it in an asynchronous setting (where edges have arbitrary response latencies) while incurring a small overhead w.r.t the number of neurons and computation time

Метод моделирования реконфигурируемых сетей на кристалле

Проведено огляд існуючих підходів до моделювання мереж на кристалі. Запропоновано метод агентного моделювання реконфігуруємих мереж на кристалі при будь-якому рівні абстракції.A review of existing approaches to modeling networks on chip is presented. The method for agent based modeling of reconfigurable networks on chip at any level of abstraction is proposed

The Design of a Network-On-Chip Architecture Based On An Avionic Protocol

When the Network-On-Chip (NoC) paradigm was introduced, many researchers have proposed many novelistic NoC architectures, tools and design strategies. In this paper we introduce a new approach in the field of designing Network-On-Chip (NoC). Our inspiration came from an avionic protocol which is the AFDX protocol. The proposed NoC architecture is a switch centric architecture, with exclusive shortcuts between hosts and utilizes the flexibility, the reliability and the performances offered by AFDX.Comment: 5 pages World Symposium on Computer Applications & Research WSCAR' 2014, 18-20 January, Sousse, Tunisi