A fast and accurate per-cell dynamic IR-drop estimation method for at-speed scan test pattern validation

ITC : 2012 IEEE International Test Conference , 5-8 Nov. 2012 , Anaheim, CA, USAIn return for increased operating frequency and reduced supply voltage in nano-scale designs, their vulnerability to IR-drop-induced yield loss grew increasingly apparent. Therefore, it is necessary to consider delay increase effect due to IR-drop during at-speed scan testing. However, it consumes significant amounts of time for precise IR-drop analysis. This paper addresses this issue with a novel per-cell dynamic IR-drop estimation method. Instead of performing time-consuming IR-drop analysis for each pattern one by one, the proposed method uses global cycle average power profile for each pattern and dynamic IR-drop profiles for a few representative patterns, thus total computation time is effectively reduced. Experimental results on benchmark circuits demonstrate that the proposed method achieves both high accuracy and high time-efficiency

A survey of scan-capture power reduction techniques

With the advent of sub-nanometer geometries, integrated circuits (ICs) are required to be checked for newer defects. While scan-based architectures help detect these defects using newer fault models, test data inflation happens, increasing test time and test cost. An automatic test pattern generator (ATPG) exercise’s multiple fault sites simultaneously to reduce test data which causes elevated switching activity during the capture cycle. The switching activity results in an IR drop exceeding the devices under test (DUT) specification. An increase in IR-drop leads to failure of the patterns and may cause good DUTs to fail the test. The problem is severe during at-speed scan testing, which uses a functional rated clock with a high frequency for the capture operation. Researchers have proposed several techniques to reduce capture power. They used various methods, including the reduction of switching activity. This paper reviews the recently proposed techniques. The principle, algorithm, and architecture used in them are discussed, along with key advantages and limitations. In addition, it provides a classification of the techniques based on the method used and its application. The goal is to present a survey of the techniques and prepare a platform for future development in capture power reduction during scan testing

CAT: A Critical-Area-Targeted Test Set Modification Scheme for Reducing Launch Switching Activity in At-Speed Scan Testing

Reducing excessive launch switching activity (LSA) is now mandatory in at-speed scan testing for avoiding test-induced yield loss, and test set modification is preferable for this purpose. However, previous low-LSA test set modification methods may be ineffective since they are not targeted at reducing launch switching activity in the areas around long sensitized paths, which are spatially and temporally critical for test-induced yield loss. This paper proposes a novel CAT (Critical-Area-Targeted) low-LSA test modification scheme, which uses long sensitized paths to guide launch-safety checking, test relaxation, and X-filling. As a result, launch switching activity is reduced in a pinpoint manner, which is more effective for avoiding test-induced yield loss. Experimental results on industrial circuits demonstrate the advantage of the CAT scheme for reducing launch switching activity in at-speed scan testing.2009 Asian Test Symposium, 23-26 November 2009, Taichung, Taiwa

DP-fill: a dynamic programming approach to X-filling for minimizing peak test power in scan tests

At-speed testing is crucial to catch small delay defects that occur during the manufacture of high performance digital chips. Launch-Off-Capture (LOC) and Launch-Off-Shift (LOS) are two prevalently used schemes for this purpose. LOS scheme achieves higher fault coverage while consuming lesser test time over LOC scheme, but dissipates higher power during the capture phase of the at-speed test. Excessive IR-drop during capture phase on the power grid causes false delay failures leading to significant yield reduction that is unwarranted. As reported in literature, an intelligent filling of don't care bits (X-filling) in test cubes has yielded significant power reduction. Given that the tests output by automatic test pattern generation (ATPG) tools for big circuits have large number of don't care bits, the X-filling technique is very effective for them. Assuming that the design for testability (DFT) scheme preserves the state of the combinational logic between capture phases of successive patterns, this paper maps the problem of optimal X-filling for peak power minimization during LOS scheme to a variant of interval coloring problem and proposes a dynamic programming (DP) algorithm for the same along with a theoretical proof for its optimality. To the best of our knowledge, this is the first ever reported X-filling algorithm that is optimal. The proposed algorithm when experimented on ITC99 benchmarks produced peak power savings of up to 34% over the best known low power X-filling algorithm for LOS testing. Interestingly, it is observed that the power savings increase with the size of the circuit

Effective Launch-to-Capture Power Reduction for LOS Scheme with Adjacent-Probability-Based X-Filling

It has become necessary to reduce power during LSI testing. Particularly, during at-speed testing, excessive power consumed during the Launch-To-Capture (LTC) cycle causes serious issues that may lead to the overkill of defect-free logic ICs. Many successful test generation approaches to reduce IR-drop and/or power supply noise during LTC for the launch-off capture (LOC) scheme have previously been proposed, and several of X-filling techniques have proven especially effective. With X-filling in the launch-off shift (LOS) scheme, however, adjacent-fill (which was originally proposed for shift-in power reduction) is used frequently. In this work, we propose a novel X-filling technique for the LOS scheme, called Adjacent-Probability-based X-Filling (AP-fill), which can reduce more LTC power than adjacent-fill. We incorporate AP-fill into a post-ATPG test modification flow consisting of test relaxation and X-filling in order to avoid the fault coverage loss and the test vector count inflation. Experimental results for larger ITC\u2799 circuits show that the proposed AP-fill technique can achieve a higher power reduction ratio than 0-fill, 1-fill, and adjacent-fill.2011 Asian Test Symposium, 20-23 November 2011, New Delhi, Indi

CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme for Reducing Yield Loss Risk in At-Speed Scan Testing

At-speed scan testing is susceptible to yield loss risk due to power supply noise caused by excessive launch switching activity. This paper proposes a novel two-stage scheme, namely CTX (Clock-Gating-Based Test Relaxation and X-Filling), for reducing switching activity when test stimulus is launched. Test relaxation and X-filling are conducted (1) to make as many FFs inactive as possible by disabling corresponding clock-control signals of clock-gating circuitry in Stage-1 (Clock-Disabling), and (2) to make as many remaining active FFs as possible to have equal input and output values in Stage-2 (FF-Silencing). CTX effectively reduces launch switching activity, thus yield loss risk, even with a small number of donpsilat care (X) bits as in test compression, without any impact on test data volume, fault coverage, performance, and circuit design.2008 17th Asian Test Symposium (ATS 2008), 24-27 November 2008, Sapporo, Japa

Maintenance Management of Wind Turbines

“Maintenance Management of Wind Turbines” considers the main concepts and the state-of-the-art, as well as advances and case studies on this topic. Maintenance is a critical variable in industry in order to reach competitiveness. It is the most important variable, together with operations, in the wind energy industry. Therefore, the correct management of corrective, predictive and preventive politics in any wind turbine is required. The content also considers original research works that focus on content that is complementary to other sub-disciplines, such as economics, finance, marketing, decision and risk analysis, engineering, etc., in the maintenance management of wind turbines. This book focuses on real case studies. These case studies concern topics such as failure detection and diagnosis, fault trees and subdisciplines (e.g., FMECA, FMEA, etc.) Most of them link these topics with financial, schedule, resources, downtimes, etc., in order to increase productivity, profitability, maintainability, reliability, safety, availability, and reduce costs and downtime, etc., in a wind turbine. Advances in mathematics, models, computational techniques, dynamic analysis, etc., are employed in analytics in maintenance management in this book. Finally, the book considers computational techniques, dynamic analysis, probabilistic methods, and mathematical optimization techniques that are expertly blended to support the analysis of multi-criteria decision-making problems with defined constraints and requirements

Damage tolerant design of additively manufactured metallic components subjected to cyclic loading:State of the art and challenges

none21siUndoubtedly, a better understanding and the further development of approaches for damage tolerant component design of AM parts are among the most significant challenges currently facing the use of these new technologies. This article presents a thorough overview of the workshop discussions. It aims to provide a review of the parameters affecting the damage tolerance of parts produced by additive manufacturing (shortly, AM parts) with special emphasis on the process parameters intrinsic to the AM technologies, the resulting defects and the residual stresses. Based on these aspects, basic concepts are reviewed and critically discussed specifically for AM materials: - Criteria for damage tolerant component design; - Criteria for the determination of fatigue and fracture properties; - Strategies for the determination of the fatigue life in dependence of different manufacturing conditions; - Methods for the quantitative characterization of microstructure and defects; - Methods for the determination of residual stresses; - Effect of the defects and the residual stresses on the fatigue life and behaviour. We see that many of the classic concepts need to be expanded in order to fit with the particular microstructure (grain size and shape, crystal texture) and defect distribution (spatial arrangement, size, shape, amount) present in AM (in particular laser powder bed fusion). For instance, 3D characterization of defects becomes essential, since the defect shapes in AM are diverse and impact the fatigue life in a different way than in the case of conventionally produced components. Such new concepts have immediate consequence on the way one should tackle the determination of the fatigue life of AM parts; for instance, since a classification of defects and a quantification of the tolerable shapes and sizes is still missing, a new strategy must be defined, whereby theoretical calculations (e.g. FEM) allow determining the maximum tolerable defect size, and non-destructive testing (NDT) techniques are required to detect whether such defects are indeed present in the component. Such examples show how component design, damage and failure criteria, and characterization (and/or NDT) become for AM parts fully interlinked. We conclude that the homogenization of these fields represents the current challenge for the engineer and the materials scientist.noneZerbst, Uwe; Bruno, Giovanni; Buffiere, Jean-Yves; Wegener, Thomas; Niendorf, Thomas; Wu, Tao; Zhang, Xiang; Kashaev, Nikolai; Meneghetti, Giovanni; Hrabe, Nik; Madia, Mauro; Werner, Tiago; Hilgenberg, Kai; Koukolíková, Martina; Procházka, Radek; Džugan, Jan; Möller, Benjamin; Beretta, Stefano; Evans, Alexander; Wagener, Rainer; Schnabel, KaiZerbst, Uwe; Bruno, Giovanni; Buffiere, Jean-Yves; Wegener, Thomas; Niendorf, Thomas; Wu, Tao; Zhang, Xiang; Kashaev, Nikolai; Meneghetti, Giovanni; Hrabe, Nik; Madia, Mauro; Werner, Tiago; Hilgenberg, Kai; Koukolíková, Martina; Procházka, Radek; Džugan, Jan; Möller, Benjamin; Beretta, Stefano; Evans, Alexander; Wagener, Rainer; Schnabel, Ka

A Capture-Safe Test Generation Scheme for At-Speed Scan Testing

Capture-safety, defined as the avoidance of any timing error due to unduly high launch switching activity in capture mode during at-speed scan testing, is critical for avoiding test- induced yield loss. Although point techniques are available for reducing capture IR-drop, there is a lack of complete capture-safe test generation flows. The paper addresses this problem by proposing a novel and practical capture-safe test generation scheme, featuring (1) reliable capture-safety checking and (2) effective capture-safety improvement by combining X-bit identification & X-filling with low launch- switching-activity test generation. This scheme is compatible with existing ATPG flows, and achieves capture-safety with no changes in the circuit-under-test or the clocking scheme.2008 13th European Test Symposium, 25-29 May 2008, Verbania, Ital