1,094 research outputs found
High-level services for networks-on-chip
Future technology trends envision that next-generation Multiprocessors Systems-on- Chip (MPSoCs) will be composed of a combination of a large number of processing and storage elements interconnected by complex communication architectures. Communication and interconnection between these basic blocks play a role of crucial importance when the number of these elements increases. Enabling reliable communication channels between cores becomes therefore a challenge for system designers. Networks-on-Chip (NoCs) appeared as a strategy for connecting and managing the communication between several design elements and IP blocks, as required in complex Systems-on-Chip (SoCs). The topic can be considered as a multidisciplinary synthesis of multiprocessing, parallel computing, networking, and on- chip communication domains. Networks-on-Chip, in addition to standard communication services, can be employed for providing support for the implementation of system-level services. This dissertation will demonstrate how high-level services can be added to an MPSoC platform by embedding appropriate hardware/software support in the network interfaces (NIs) of the NoC. In this dissertation, the implementation of innovative modules acting in parallel with protocol translation and data transmission in NIs is proposed and evaluated. The modules can support the execution of the high-level services in the NoC at a relatively low cost in terms of area and energy consumption. Three types of services will be addressed and discussed: security, monitoring, and fault tolerance. With respect to the security aspect, this dissertation will discuss the implementation of an innovative data protection mechanism for detecting and preventing illegal accesses to protected memory blocks and/or memory mapped peripherals. The second aspect will be addressed by proposing the implementation of a monitoring system based on programmable multipurpose monitoring probes aimed at detecting NoC internal events and run-time characteristics. As last topic, new architectural solutions for the design of fault tolerant network interfaces will be presented and discussed
Security of Electrical, Optical and Wireless On-Chip Interconnects: A Survey
The advancement of manufacturing technologies has enabled the integration of
more intellectual property (IP) cores on the same system-on-chip (SoC).
Scalable and high throughput on-chip communication architecture has become a
vital component in today's SoCs. Diverse technologies such as electrical,
wireless, optical, and hybrid are available for on-chip communication with
different architectures supporting them. Security of the on-chip communication
is crucial because exploiting any vulnerability would be a goldmine for an
attacker. In this survey, we provide a comprehensive review of threat models,
attacks, and countermeasures over diverse on-chip communication technologies as
well as sophisticated architectures.Comment: 41 pages, 24 figures, 4 table
A Path to Peace: Thoughts on Olympic Revenue and the IOC/USOC Divide
U.S. Public Law 95-606 (otherwise known as the Amateur Sports Act), passed in 1978, has contributed significantly to the relationship between the United States Olympic Committee (USOC) and the International Olympic Committee (IOC) for the past thirty years. Exclusive rights to the use of Olympic marks and emblems in the U.S. territory granted to it in the Amateur Sports Act were leveraged by the USOC to obtain amounts of Olympic generated revenue from the sale of television rights fees and major corporate sponsorships far larger than any of the other National Olympic Committees (NOCs) recognized by the IOC. This privileged financial position has become a divisive issue for the USOC, IOC, and the world’s 204 other NOCs. The IOC and USOC have agreed to commence discussions towards the establishment of a revised method to distribute Olympic revenue to members of the Olympic Tripartite (IOC, NOCs, and International Sport Federations). We suggest broadening this discussion to include a move to increase the amount of money from these sources transferred to Olympic Organizing Committees (OCOGs) to support a more formalized legacy plan for Olympic athletic facilities in host cities, and adding a new sponsor category to the existing corporate sponsorship program, The Olympic Partners (TOP), to enhance the IOC’s commitment to social responsibility and sustainability. We also propose a new formula for the distribution of Olympic television and corporate sponsorship revenue as a means of contributing to this dialogue that must target a mutually acceptable resolution in order to foster a more harmonious working relationship between the IOC and USOC
Runtime Detection of a Bandwidth Denial Attack from a Rogue Network-on-Chip
Chips with high computational power are the crux of today’s pervasive complex digital systems. Microprocessor circuits are evolving towards many core designs with the integration of hundreds of processing cores, memory elements and other devices on a single chip to sustain high performance computing while maintaining low design costs. Two decisive paradigm shifts in the semiconductor industry have made this evolution possible: (a) architectural and (b) organizational.
At the heart of the architectural innovation is a scalable high speed data communication structure, the network-on-chip (NoC). NoC is an interconnect network for the glueless integration of on-chip components in the modern complex communication centric designs. In the recent days, NoC has replaced the traditional bus based architecture owing to its structured and modular design, scalability and low design cost. The organizational revolution has resulted in a globalized and collaborative supply chain with pervasive use of third party intellectual properties to reduce the time-to-market and overall design costs.
Despite the advantages of these paradigm shifts, modern system-on-chips pose a plethora of security vulnerabilities. This work explores a threat model arising from a malicious NoC IP embedded with a hardware trojan affecting the resource availability of on-chip components. A rigorous simulation infrastructure is established to evaluate the feasibility and potency of such an attack. Further, a non-invasive runtime monitoring technique is proposed and thoroughly investigated to ensure the trustworthiness of a third party NoC IP with low overheads
Performance Implications of NoCs on 3D-Stacked Memories: Insights from the Hybrid Memory Cube
Memories that exploit three-dimensional (3D)-stacking technology, which
integrate memory and logic dies in a single stack, are becoming popular. These
memories, such as Hybrid Memory Cube (HMC), utilize a network-on-chip (NoC)
design for connecting their internal structural organizations. This novel usage
of NoC, in addition to aiding processing-in-memory capabilities, enables
numerous benefits such as high bandwidth and memory-level parallelism. However,
the implications of NoCs on the characteristics of 3D-stacked memories in terms
of memory access latency and bandwidth have not been fully explored. This paper
addresses this knowledge gap by (i) characterizing an HMC prototype on the
AC-510 accelerator board and revealing its access latency behaviors, and (ii)
by investigating the implications of such behaviors on system and software
designs
Dynamic Security-aware Routing for Zone-based data Protection in Multi-Processor System-on-Chips
In this work, we propose a NoC which enforces the
encapsulation of sensitive traffic inside the asymmetrical security
zones while using minimal and non-minimal paths. The NoC
routes guarantee that the sensitive traffic is communicated only
through the trusted nodes which belong to the security zone.
As the shape of the zones may change during operation, the
sensitive traffic must be routed through low-risk paths. We test
our proposal and we show that our solution can be an efficient
and scalable alternative for enforce the data protection inside the
MPSoC
A Survey of Software-Defined Networks-on-Chip: Motivations, Challenges and Opportunities
Current computing platforms encourage the integration of thousands of processing cores,
and their interconnections, into a single chip. Mobile smartphones, IoT, embedded devices, desktops,
and data centers use Many-Core Systems-on-Chip (SoCs) to exploit their compute power and
parallelism to meet the dynamic workload requirements. Networks-on-Chip (NoCs) lead to scalable
connectivity for diverse applications with distinct traffic patterns and data dependencies. However,
when the system executes various applications in traditional NoCs—optimized and fixed at synthesis
time—the interconnection nonconformity with the different applications’ requirements generates
limitations in the performance. In the literature, NoC designs embraced the Software-Defined
Networking (SDN) strategy to evolve into an adaptable interconnection solution for future chips.
However, the works surveyed implement a partial Software-Defined Network-on-Chip (SDNoC)
approach, leaving aside the SDN layered architecture that brings interoperability in conventional
networking. This paper explores the SDNoC literature and classifies it regarding the desired SDN
features that each work presents. Then, we described the challenges and opportunities detected
from the literature survey. Moreover, we explain the motivation for an SDNoC approach, and we
expose both SDN and SDNoC concepts and architectures. We observe that works in the literature
employed an uncomplete layered SDNoC approach. This fact creates various fertile areas in the
SDNoC architecture where researchers may contribute to Many-Core SoCs designs.Las plataformas informáticas actuales fomentan la integración de miles de núcleos de procesamiento
y sus interconexiones, en un solo chip. Los smartphones móviles, el IoT, los dispositivos embebidos, los ordenadores de sobremesa y los centros de datos utilizan sistemas en chip (SoC) de muchos núcleos para explotar su potencia de cálculo y paralelismo para satisfacer los requisitos de las cargas de trabajo dinámicas. Las redes en chip (NoC) conducen a una conectividad escalable para diversas aplicaciones con distintos patrones de tráfico y dependencias de datos. Sin embargo, cuando el sistema ejecuta varias aplicaciones en las NoC tradicionales -optimizadas y fijadas en el momento de sÃntesis, la disconformidad de la interconexión con los requisitos de las distintas aplicaciones genera limitaciones en el rendimiento. En la literatura, los diseños de NoC adoptaron la estrategia de redes definidas por software (SDN) para evolucionar hacia una solución de interconexión adaptable para los futuros chips.
Sin embargo, los trabajos estudiados implementan un enfoque parcial de red definida por software en el chip (SDNoC) de SDN, dejando de lado la arquitectura en capas de SDN que aporta interoperabilidad en la red convencional. Este artÃculo explora la literatura sobre SDNoC y la clasifica en función de las caracterÃsticas SDN que presenta cada trabajo. A continuación, describimos los retos y oportunidades detectados a partir del estudio de la literatura. Además, explicamos la motivación para un enfoque SDNoC, y
exponemos los conceptos y arquitecturas de SDN y SDNoC. Observamos que los trabajos en la literatura
emplean un enfoque SDNoC por capas no completo. Este hecho crea varias áreas fértiles en la
arquitectura SDNoC en las que los investigadores pueden contribuir a los diseños de SoCs de muchos núcleos
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